Ultra high speed complementary MOS device

Details Ultra high speed complementary MOS device Ultra high speed complementary MOS device

1979-02-09

1980-10-21

Wojciechowicz, Edward J.

357 23, 357 41, 357 46, 357 55, 357 56, H01L 2702

Patent

active

042297567

ABSTRACT:
An improved, ultra high speed (2GHz) CMOS inverter structure comprising a double-diffused, planar p-channel transistor and a nonplanar n-channel transistor formed within adjacent surface fields on the same substrate. The n-channel device includes a source region formed in an elevated, plateau region on the substrate, and a narrow, implanted channel-forming layer that extends through the plateau beneath the source region and terminates at a slope joining the plateau to surrounding lower elevation portions of the substrate. A drain region is formed adjacent the foot of the slope, spaced from the channel to provide a drift region between them.

REFERENCES:
patent: 3823352 (1974-07-01), Pruniaux et al.
patent: 4063274 (1977-12-01), Dingwall
Electronics-Dec. 7, 1978, pp. 41-42.

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