Ultra high speed clocked analog latch

Details Ultra high speed clocked analog latch Ultra high speed clocked analog latch

2001-05-25

2003-09-09

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S200000, C327S201000

Reexamination Certificate

active

06617899

ABSTRACT:

BACKGROUND OF THE INVENTION
The field of the invention relates to disk drives and other data storage devices. More particularly, this invention relates to disk drives having read/write channels with analog to digital converters. An analog latch is the basic building block for a high-speed analog-to-digital converter (ADC). This circuit makes a comparison between an input analog voltage signal and an internally generated reference voltage. The output of the analog latch is a digital signal, high or low, depending on whether the input voltage is higher than the reference voltage. Many such latches are used, in combination with other circuits, in forming an ADC.
FIG. 1
is a high-level block diagram of a 6-bit flash analog-to-digital converter (ADC)
100
. The ADC includes an autozero control and clock generator module
102
, which is connected to each of 63 analog latches
108
. Each analog latch receives also an input analog voltage signal
104
and a reference voltage signal
106
. Signals
104
and
106
may be differential signals. The high or low outputs of the latches
108
are sent to logic circuitry
110
. Afterwards, the converted digital signals may be used in ROM
112
for ADC output, and may be used in a register
114
by other circuitry. One possible use for ADCs such as this one is for read/write operations in computers or computer peripherals or logic circuitry.
BRIEF SUMMARY
An ultra high-speed clocked analog latch is disclosed. The analog latch is used as a latching comparator for comparing a time-varying analog signal with an analog reference voltage. This latch is particularly useful in analog-to-digital converters (ADCs) having an auto-zero operation or capability. The clocked analog latch has a first clocked preamplifier, a second clocked preamplifier, a signal level shifter, at least one differential analog latch stage, and an RS latch stage. The circuit is designed for a high-speed, time varying clocked operation, including rates from about 100 MHz to several GHz.
The first clocked preamplifier receives a differential analog signal and subtracts a differential reference voltage from it. It preamplifies the resulting difference signal by a gain factor of 5 to 10. The second clocked preamplifier receives the preamplified signal of the first preamplifier and performs a second preamplification operation on the signal, for an additional gain factor of 3 to 5. The two preamplifiers together produce a gain of from 15 to 50 for a small input differential signal. While the preamplifiers are high speed, they are limited in their output voltage swing, so that a maximum output voltage from the preamplifiers is about 100-200 millivolts. An output signal from the preamplifiers may then be connected to a level shifter, to shift the absolute voltage level of the signal, with respect to a reference, such as a ground. The output of the preamplifiers is aimed primarily at discerning whether the input signal was greater or smaller than a reference voltage applied to the preamplifier.
The shifted voltage signal is then processed by at least one clocked analog latch stage. The analog stages have a very high gain, but the gain is limited to that which is possible in a very short period of time, such as about 1 nanosecond. The output of one or more analog latch stages is a voltage signal of about zero to 0.1 volts or is about 0.7 volts. This signal is transmitted to an RS latch, where the signal remains during the following reset state of the previous latch stage. The signal on the RS latch is the output of the high speed clocked analog latch, read and used by other components of a read/write circuit, as shown in FIG.
1
.


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patent: 6278308 (2001-08-01), Partovi et al.
patent: 6366113 (2002-04-01), Song
“Synchronous Recording Channels—PRML & Beyond”, rev. 5.61 14.E.18, 1999, published by Knowledge Tek, Inc., Broomfield, Colorado.
“PRML: Seagate Uses Space Age Technology” available on the Internet at http://www.seagate.com/support/kb/disc/prml.html, 2 pages, last accessed Apr. 9, 2001.
“Technologies—PRML” available on the Internet at http://www.idema.org/about/industry/ind-tech-prml.html, 1 page, last accessed Apr. 9, 2001.
“Reference Guide—Hard Disk Drives” available on the Internet at http://www.storagereview.com/guide2000/ref/hdd, 13 pages, last accessed Apr. 9, 2001.
“MR and PRML: Technologies in Synergy” available at on the Internet at http://www.lionsgate.com/Home/Baden/public-html-index/SCSI/Quantum-White-Papers/MR-Head/MR, 4 pages, last accessed Apr. 9, 2001.
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