Ultra-high-density pass gate using dual stacked transistors havi

Details Ultra-high-density pass gate using dual stacked transistors havi Ultra-high-density pass gate using dual stacked transistors havi

1997-08-01

1999-09-07

Abraham, Fetsum

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257241, 257330, 257332, 257368, 257377, 257385, 438153, 438158, H01L 2978

Patent

active

059490926

ABSTRACT:
A multi-dimensional transistor structure is fabricated which includes a base transistor substrate upon which transistors are formed. An elevated substrate is formed overlying the base transistor and having an oxide isolation formed in localized regions beneath the elevated substrate but overlying the base transistor substrate. A plurality of transistors are formed on a substrate wafer to form a base-level transistor formation. An intralevel dielectric (ILD) layer is deposited overlying the base-level transistor formation. Overlying the ILD layer, a "sandwich" structure is formed with the deposition of a first polysilicon layer, deposition of an oxide isolation layer, and deposition of a second polysilicon layer. The median oxide isolation layer is patterned and etched according to a localized oxide isolation mask in a configuration determined by the position of transistors in the base-level transistor formation and by the planned position of transistors, that are not yet formed, in an overlying elevated substrate level. The median oxide isolation layer is patterned and etched in a configuration so that isolation is achieved in a predetermined manner, for example, on an individual transistor basis, a transistor group basis, or the like. The resulting electronic integrated circuit structure is used for high speed circuit applications due to high packing densities and small distances between devices.

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