Ultra high density integrated circuit BLP stack and method...

Details Ultra high density integrated circuit BLP stack and method... Ultra high density integrated circuit BLP stack and method...

2001-05-04

2002-06-04

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C257S686000, C257S696000

Reexamination Certificate

active

06399420

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a BLP stack of ultra-high density integrated circuits and a method for fabricating the same, and more particularly, to a BLP stack of ultra-high density integrated circuits and a method for fabricating the same which is made lighter, thinner, shorter, and smaller with a higher reliability and a less area of mounting for providing a denser package.
2. Discussion of the Related Art
In general, packaging techniques for integrated circuits have been developed in the past in an attempt to satisfy demands for miniaturization in the semiconductor industry. Improved methods for miniaturization of integrated circuits enabling the integration of millions of circuit elements into single integrated silicon embodied circuits, or chips, have resulted in increased emphasis on methods to package theses circuits in space efficient, yet reliable and mass producible packages.
FIGS. 1
a
~
3
c
illustrates the steps of fabricating processes for obtaining stacks of semiconductor packages of which memory sizes are extended by stacking completed packages into a memory size extended semiconductor package stack. The steps of process for fabricating a background art TSOP(Thin Small Outline Package) stack
5
will be explained.
Referring to
FIGS. 1
a
and
1
b,
a top, and a bottom TSOPs
50
are provided. As shown in
FIG. 2
b,
both bent outer leads
500
on each of the TSOPs
50
are straightened as shown in
FIG. 2
b,
and cut far ends only leaving short lengths as shown in
FIG. 2
c.
Then, the TSOPs
50
are stacked and bonded together with the leads aligned as shown in
FIG. 3
a.
There is adhesive
501
applied between the top, and bottom TSOPs
50
. As shown in
FIG. 3
b,
stacking rails
510
having holes
511
for inserting and connecting the outer leads
500
of the TSOPs
50
thereto are provided, the holes
510
in the stacking rails
510
and fore ends of the outer leads
500
on the bonded TSOPs
50
are aligned, and the outer leads
500
on the TSOPs
50
are inserted into the holes
511
in the rails
510
. Then, adhesive
503
is applied to an underside of a top parts of the rails
510
and the rails
510
and a top surface of the TSOP
50
are attached, preventing movement of the rails
510
. Solder paste
502
is applied to upper sides of the holes
511
in the rails
510
and heated so that the solder paste
502
bonds the rails
510
and the outer leads
500
together. Instead of using the solder paste in the bonding, the bonding parts may be dipped into molten solder.
Thus, by the mechanical and electrical connection of the two packages, a TSOP stack
5
is completed, with a doubled memory capacity, i.e., a memory capacity of the package stack may be varied by stacking the TSOPs
50
as many as desired according to a memory capacity required. For example, if an 8-mega DRAM package stack is desired from 4-mega DRAM TSOPs, two of the 4-mega DRAM TSOPs are stacked, and if a 16-mega DRAM package stack is desired from 4-mega DRAM TSOPs, four of the 4-mega DRAM TSOPs are stacked.
FIG. 5
illustrates another example of background art stacked package for providing a package stack
6
thin, yet durable, resistant against mechanical distortion from moist and warping, and heat dissipative, disclosed in U.S. Pat. No. 5,446,620 in detail.
However, the background art simple package stack of chip packages results in the stack bulky and heavy. Also, the background art package stack has problems in that connections with the rails
510
are exposed and not satisfactory in strength, that degrades a reliability. And, the long signal lines from bonding pads on the semiconductor chip
7
to a printed circuit board(the outer leads and the rails) can cause a signal delay which hamper a fast performance, or a greater interference noise, degrading a reliability in terms of electrical performance. On the other hand, in the fabrication process, the repetitive adhesive bonding steps may cause distortion of components or weaken a bonding force between the semiconductor chip and the mold body. And, the increased number of fabrication steps due to the additional stacking of the completed packages, and the requirement for separate stacking equipments other than the equipments required for fabrication of the completed package requires additional cost and longer fabrication time period. Particularly, in the case of TSOP stack
5
, the steps of process for stacking the packages are very complicated with straightening and cutting unnecessary portions of outer leads of completed TSOPs
50
, separate fabrication of the rails
510
, and alignment of leads
500
between the top and bottom TSOPs
50
for inserting the leads
500
into the holes
511
in the fabricated rails
510
as well as attachment of the rails on a top surface of the package.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed an ultra-high density integrated circuit BLP stack and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a semiconductor package stack which has a high density and short signal lines, with excellent mechanical and electrical reliability.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the BLP stack of ultra-high density integrated circuit includes a three dimensional BLP having external power connection leads each started to be exposed through a bottom thereof and extended to surround a bottom surface, a side surface, and a top surface of a body of the package, and a standard BLP having bottom leads brought into contact with the bottom leads of the BLP, thereby being stacked on the three dimensional BLP.
In a second aspect of the present invention, there is provided a BLP stack of ultra-high density integrated circuit, including at least two three dimensional BLPs stacked in succession such that lead portions of an overlying three dimensional BLP and leads on an underlying three dimensional BLP are connected electrically to each other, the three dimensional BLPs having external power connection leads each started to be exposed through a bottom thereof and extended to bend around to surround a bottom surface, a side surface, and a top surface of a body of the package.
In a third aspect of the present invention, there is provided a BLP stack including a first BLP stack and a second BLP stack identical to the first BLP stack disposed opposite to the first BLP such that the bottom leads portions of the
3
D BLP in the second BLP stack are brought into contact with the bottom lead portions of the
3
D BLP in the first BLP stack, the first BLP stack having a
3
D BLP with external power connection leads each started to be exposed through a bottom thereof and extended to bend around to surround a bottom surface, a side surface, and a portion of a top surface thereof and a standard type BLP stacked on the
3
D BLP such that bottom leads of the standard BLP is electrically connected to upper lead portions exposed in an upper surface of a body of the
3
D BLP.
In a fourth aspect of the present invention, there is provided a BLP stack including a
3
D BLP having external power connection leads each started to be exposed through a bottom thereof and extended to bend around to surround a bottom surface, a side surface, and a portion of a top surface thereof, a standard type BLP placed on the bottom lead portions on the
3
D BLP such that the bottom leads are electrically brought into contact with upper lead

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