Ulsi mask ROM structure and method of manufacture

Details Ulsi mask ROM structure and method of manufacture Ulsi mask ROM structure and method of manufacture

1994-08-29

1995-01-17

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read only systems

Semiconductive

365174, 365176, 365182, 365178, 257369, 257390, 257391, 257392, G11C 1712

Patent

active

053831497

ABSTRACT:
A ROM device provides a double density memory array. The word line array is composed of transversely disposed conductors sandwiched between two arrays of bit lines which are orthogonally disposed relative to the word line array. The two arrays of bit lines are stacked with one above and with one below the word line array. A first gate oxide layer is located between the word line array and a first one of the array of bit lines and a second gate oxide layer is located between the word line array and a the other of the arrays of bit lines. The two parallel sets of polysilicon thin, film transistors are formed with the word lines serving as gates for the transistors.

REFERENCES:
patent: 4555721 (1985-11-01), Bansal et al.
patent: 5017978 (1991-05-01), Middelhoek et al.
patent: 5025494 (1991-06-01), Gill et al.

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