Type II phase locked loop using dual path and dual varactors...

Details Type II phase locked loop using dual path and dual varactors... Type II phase locked loop using dual path and dual varactors...

2005-12-05

2008-03-18

Chang, Joseph (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S016000

Reexamination Certificate

active

07345550

ABSTRACT:
A phase locked loop (PLL) with reduced loop filter components having dual charge pumps and corresponding dual signal paths that reduce on-chip component size within the filters. The dual paths are combined advantageously via dual varactors within a voltage controlled oscillator to further reduce loop filter components. The PLL removes the drawbacks of noise introduced by circuitry normally used for summing dual path configurations.

REFERENCES:
patent: 6281758 (2001-08-01), Elsayed et al.
patent: 2002/0075091 (2002-06-01), Lo et al.
Herzel et al., An Integrated CMOS RF Synthesizer for 802.11a Wireless LAN, IEEEJournal of Solid-State Circuits, vol. 38, No. 10, 2003, pp. 1767-1770.
Lee et al., “A Stabilization Technique for Phase-Locked Frequency Synthesizers”,IEEE Journal of Solid-State Circuits, vol. 38, No. 6, 2003, pp. 888-894.

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