Two-wire bus-system comprising a clock wire and a data wire for

Details Two-wire bus-system comprising a clock wire and a data wire for Two-wire bus-system comprising a clock wire and a data wire for

1981-11-02

1987-08-25

Shaw, Gareth D.

Boots, shoes, and leggings

364900, G06F 1342

Patent

active

046897402

ABSTRACT:
A computer system comprises a number of stations which are interconnected by means of a clock bus wire (20) and a data bus wire (22) which both form a wired logic function of the signals generated thereon by the stations (32, 34). During the clock pulses, the signal on the data bus wire is stationary; it may change between the clock pulses. Start and stop conditions are formed by a signal combination between clock bus wire and data bus wire (60 and 62, respectively) which is not permissible in a data stream. If there is more than one master station so that a composite clock signal occurs on the clock bus wire, the clocks of the relevant master stations are each time resynchronized to the actual transitions in the composite clock signal.

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patent: 4101732 (1978-07-01), Suzuki
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