Two-transistor flash memory device using replica cell array...

Details Two-transistor flash memory device using replica cell array... Two-transistor flash memory device using replica cell array...

2007-08-28

2007-08-28

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170, C365S185200, C365S203000, C365S210130

Reexamination Certificate

active

11177355

ABSTRACT:
A semiconductor memory device includes a memory cell array, first bit lines, second bit lines, a first precharge circuit, a sense amplifier, and a read control circuit. The memory cell array has a first cell array including first memory cells arranged in a matrix and a second cell array including second memory cells. The first bit line electrically connects the first memory cells in a same column. The second bit line electrically connects the second memory cells in a same column. The first precharge circuit precharges the first bit lines in a read operation. The sense amplifier amplifies the data read from the first memory cells in a read operation. The read control circuit precharges and discharges the second bit lines in a read operation and, on the basis of the time required to precharge and discharge the second bit lines, controls the first precharge circuit and the sense amplifier.

REFERENCES:
patent: 5325337 (1994-06-01), Buttar
patent: 6630707 (2003-10-01), Shinmori
Nobuaki Otsuka, et al., “Circuit Techniques for 1.5-V Power Supply Flash Memory”, IEEE Journal of Solid-State Circuits, vol. 32, No. 8, Aug. 1997, pp. 1217-1230.
Rino Micheloni, et al., “The Flash Memory Read Path: Building Blocks and Critical Aspects”, Proceedings of the IEEE, vol. 91, No. 4, Apr. 2003, pp. 537-553.
Wei-Hua Liu, et al., “A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8V-Only Applications”, Non-Volatile Semiconductor Memory Workshop 4.1, 1997, pp. 1-3.

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