Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-12-14
2004-06-29
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185050, C365S185180, C365S185240, C365S185260, C365S085000, C365S185290, C365S185330
Reexamination Certificate
active
06757196
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory and in particular to a two transistor flash EEPROM cell for use in low-voltage, low-power, high-speed, and high-density applications, such as complex programmable logic devices.
2. Description of the Related Art
Prior art Flash memory technology used in applications for devices, such as PLD (programmable Logic Device), PAL (programmable array logic) and EPLD (erasable programmable logic device), are two transistor memory cells comprised of an NMOS nonvolatile memory device and an NMOS access device. These two transistors are connected in series to form the basic flash memory cell for programmable logic devices. The NMOS nonvolatile memory device of prior art is an asymmetric device with respect to the source and drain as well as operating conditions. A high voltage is required across the drain and source region during programming which requires a longer channel gate length to prevent punch through. This causes a physical limitation on how small the cell can be made and in turn limits the use of the cell in ultra high integration levels of the flash memory below 0.18 um technology.
U.S. Pat. No. 6,108,239 (Sekariapuram et al.) is directed toward a compact nonvolatile programmable memory cell which has a substantially transverse or vertical channel relative to the surface of the semiconductor substrate. In U.S. Pat. No. 6,078,521 (Madurawe et al.) a nonvolatile memory cell is directed toward a compact layout and a high logic output voltage. In U.S. Pat. No. 5,914,904 (Sansbury) is directed toward a nonvolatile memory cell that has a read device, a program device and a tunnel diode. In U.S. Pat. No. 5,904,524 (Smolen) a device and method is directed toward an EEPROM device that has a self aligned tunnel window with low gate capacitance and avoids defects caused by field oxide induced stress in the tunnel oxide. In U.S. Pat. No. 5,914,514 (Dejenfelt et al.) a flash EEPROM cell is directed toward a two transistor cell for high speed and high density PLD applications. The storage transistor is directed toward preventing problems with over erase and punch through, and allows scaling the gate length to allow 5V cell programming.
In U.S. Pat. No. 5,862,082 (Dejenfelt et al.) a device is directed toward a flash EEPROM cell that has two transistors with one transistor being a floating gate type device with asymmetric source and drain. In
FIG. 1
is shown a cross sectional view of prior art for aflash EEPROM cell
100
similar to that of U.S. Pat. No. 5,862,082. The flash EEPROM cell includes a nonvolatile memory transistor
101
and an access transistor
102
. The nonvolatile memory transistor
101
is fabricated within a p-well
103
and is a stack type double poly transistor, which includes a thin tunnel oxide film
108
, a floating gate
109
, an interpoly dielectric layer
110
, a control gate
113
, n+ source region
123
, n+ source/drain region
122
and n− type region
124
. The access transistor
102
is fabricated within a p-well
103
, which includes a source/drain region
122
, n+ drain region
121
, a gate dielectric layer
111
and an access gate
112
. The P-well
103
is formed within an n-well
104
, which is formed on a p-substrate
105
. A field oxide layer
120
is formed over the upper surface of the substrate
105
. An N+ type region
106
is formed in the n-well
104
creating a contact region for the N-well. A P+type region
107
is formed in p-well
103
creating a contact region for the P-well.
FIG. 2
of the prior art is a circuit diagram illustrated as a 2×2 array
600
, formed by a plurality of identical flash EEPROM cells
601
,
602
,
603
and
604
, which are comprised of the flash EEPROM cell
100
. Each column of cells has separate source lines
631
and
641
and drain bit lines
632
and
642
for high-speed PLD applications. Lines
611
and
621
connect to the control gates of the storage transistors of cells
601
and
602
, and cells
603
and
604
respectively. Lines
612
and
622
connect to the access gates of the access transistors of cells
601
and
602
, and cells
603
and
604
respectively.
FIG.3
is a plane view of prior art of the flash EEPROM cells
601
to
604
of array
600
, and corresponding to the circuit diagram in FIG.
2
. Control gate lines
611
and
621
run horizontal across the plane view of the cells connecting to the control gates of the storage transistors of cells
601
and
602
, and cells
603
and
604
respectively. Similarly access lines
612
and
622
run horizontally across the plane view of the cells connecting to the gates of the access transistors of cells
601
and
602
, and cells
603
and
604
respectively. Source lines
631
and
641
run vertically across the plane view connecting to the sources of the storage transistors of the EEPROM cells
601
and
603
, and cells
602
and
604
respectively. Similarly bit lines
632
and
642
run vertically across the plane view connecting to the sources of the storage transistors of the EEPROM cells
601
and
603
, and cells
602
and
604
respectively.
FIG. 4
is a table for the prior art illustrating the voltage conditions for program, program inhibit, erase and read operation for array
600
. Both erase and program operations use the Fowler-Nordheim tunneling. The electrons are injected into the floating gate of the storage transistor of the cells by channel-erase operation which increases the threshold voltage Vt) of the storage transistor. The electrons are extracted out of the floating gate of the storage transistor by an edge-program operation which decreases Vt. The erase operation is performed in a blanket mode. All the cells
601
-
604
in array
600
are erased simultaneously. A high voltage of 8 to 10 volts is applied to the control gate word lines
611
and
621
, and a negative high voltage of −8 to −10 volts is applied to source lines
631
and
641
. At the same time, the same negative high voltage −8 to −10 volts is applied to p-well
103
, and Vcc supply voltage of 3.3 volts is applied to n-welll
04
. Thus the threshold voltage Vt of the storage transistor of the cells is increased for the erase operation.
Continuing to refer to
FIG. 4
, a program operation is performed bit by bit on each word line. For example, cell
601
is programmed and cell
602
is program inhibited by applying a voltage of −7 to −11 volts to the control gate word line
611
and applying a voltage of 8 volts is to the access gate
612
. The source lines
631
and
641
are maintained at a high impedance state, and a voltage of 5 to 8 volts is applied to the bit line
632
with 0 volt applied to the bit line
642
. P-well
103
is maintained at 0V and the n-well
104
is maintained at the Vcc supply voltage, 3.3 volts. As a result, cells
601
and
602
are placed in the program and program inhibition mode, respectively.
Continuing to refer to
FIG. 4
, the two-transistor flash EEPROM cell of prior art created with an n+ source/drain region
122
and an n− type region
124
that are made to be much deeper than the n+ source junction
123
, which is surrounded with lightly-doped N-implant to reduce the peak electrical field generated during drain-edge-program operation. For programming purposes, it should be noted that there is a reverse bias voltage between n− type region
124
and p-well
103
. As a result of the negative high voltage applied to the gate of the memory cell, electron-hole pairs will be generated and holes are accelerated onto the floating gate under the high electrical field. A certain amount of holes will be trapped in the tunnel oxide, and will degrade the oxide after cycling.
The memory cell of prior art is made non-symmetrical with respect to source and drain junctions in terms of cell structure and operating conditions. A high voltage of more than 5V across lightly doped N implant drain region and source region during program operation is r
Hsu Fu-Chang
Lee Peter W.
Tsao Hsing-Ya
Ackerman Stephen B.
Aplus Flash Technology Inc.
Saile George O.
Yoha Connie C.
LandOfFree
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