Two transistor flash EPROM cell

Details Two transistor flash EPROM cell Two transistor flash EPROM cell

1993-03-08

1994-07-12

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

365174, 365218, G11C 1140

Patent

active

053294874

ABSTRACT:
A two-transistor flash EPROM cell includes a first floating gate transistor for programming the cell and a second merged transistor for reading the cell. The first transistor, a floating gate transistor, has a drain coupled to the write bit line, a gate coupled to the word line, and a source coupled to the source line. The merged transistor effectively consists of a floating gate transistor in series with a NMOS enhancement transistor. The series NMOS transistor has a voltage threshold of about 1 to 2 volts, thus preventing cell activation caused by overerasure (negative voltage threshold) of the floating gate transistor.

REFERENCES:
patent: 4403307 (1983-09-01), Maeda
patent: 5220533 (1993-06-01), Turner
Pathak et al., "A 25ns 16K CMOS PROM using a 4-Transistor Cell," Session XIII: Nonvolatile Memories--ISSCC 1985, Feb. 14, 1985, pp. 162-164.
Pathak et al., "A 19ns 250mW Programmable Logic Device," Session XVIII: Logic Arrays and Memories--ISSCC 1986, Feb. 21, 1986, pp. 246-247.
Samachisa et al., "A 128K Flash EEPROM using Double Polysilicon Technology," Session VII: Nonvolatile Memory--ISSCC 1987, Feb. 25, 1987, pp. 76-77.
Kynett et al., "A 90ns 100K Erase/Program Cycle Megabit Flash Memory," Session 10. Nonvolatile Memories--ISSCC 1989, Feb. 16, 1989, pp. 140-141.

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