Static information storage and retrieval – Floating gate – Particular biasing
Patent
1998-04-16
1999-01-19
Fears, Terrell W.
Static information storage and retrieval
Floating gate
Particular biasing
36518528, G11C 1300
Patent
active
058620826
ABSTRACT:
A flash electrically erasable programmable read only memory (EEPROM) cell fabricated in a semiconductor substrate. A first well region having a first conductivity type is located in the semiconductor substrate. A second well region having a second conductivity type, opposite the first conductivity type, is located in the first well region. A non-volatile memory transistor and an independently controllable access transistor are fabricated in the second well region. The non-volatile memory transistor and the access transistor are connected in series, such that the source of the access transistor is coupled to the drain of the non-volatile memory transistor. The first well region, the second well region, the non-volatile memory transistor and the access transistor are biased such that electrons are transferred from the first well region to a floating gate of the non-volatile memory transistor by Fowler-Nordheim tunneling during an erase mode, and electrons are transferred from the floating gate of the non-volatile memory transistor through the access transistor by Fowler-Nordheim tunneling during a program mode. None of the biasing voltages exceed 12 Volts, thereby enabling the flash EEPROM cell to operate in a 3.3 Volt system. In one embodiment, an array of flash EEPROM cells are fabricated in the second well region.
REFERENCES:
patent: 3986054 (1976-10-01), Hansen et al.
patent: 4577295 (1986-03-01), Eitan et al.
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 5162680 (1992-11-01), Norman et al.
patent: 5218568 (1993-06-01), Lin et al.
patent: 5313427 (1994-05-01), Schreck et al.
patent: 5329487 (1994-07-01), Gupta et al.
patent: 5379253 (1995-01-01), Bergemont
patent: 5432740 (1995-07-01), D'Arrigo et al.
patent: 5453388 (1995-09-01), Chen et al.
patent: 5471422 (1995-11-01), Chang et al.
patent: 5530384 (1996-06-01), Lee et al.
patent: 5559735 (1996-09-01), Ono et al.
patent: 5563827 (1996-10-01), Lee et al.
patent: 5631583 (1997-05-01), Lee et al.
patent: 5687118 (1997-11-01), Chang
D. Bursky, "Flash EEPROM Takes Changes in Place by Cutting Programming Signal to 5V", Electronic Design, vol. 37, No. 23, 9 Nov. 1989, p. 30.
Dejenfelt Anders T.
Diba Sholeh
Hoffstetter Diane M.
Lin Qi
Olah Robert A.
Fears Terrell W.
Harms Jeanette S.
Hoffman E. Eric
Xilinx , Inc.
LandOfFree
Two transistor flash EEprom cell and method of operating same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Two transistor flash EEprom cell and method of operating same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Two transistor flash EEprom cell and method of operating same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1252007