Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-05-02
2006-05-02
Auduong, Gene N. (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185010, C365S185270
Reexamination Certificate
active
07038947
ABSTRACT:
An nonvolatile memory device having improved endurance is comprised of an array of nonvolatile memory cells arranged in rows and columns. Each memory cell is composed of a program transistor and read transistor with a control gate connected to a word line, a source connected the source select line, and a floating gate onto which an electronic charge is placed representing a data bit stored within the nonvolatile memory device. The program transistor has a drain connected a first bit line and a read transistor has a drain connected to the second bit line. Each memory cell has a floating gate connector joining the floating gate of the read transistor to the floating gate of the read transistor. The nonvolatile memory device has a voltage controller that programs the each memory cell by programming the program transistor and reading the read transistor.
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Auduong Gene N.
Duane Morris LLP
Taiwan Semiconductor Manufacturing Co. Ltd.
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