Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-12-19
2004-08-24
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185270, C365S185290
Reexamination Certificate
active
06781881
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a class of nonvolatile memory devices referred to as flash electrically erasable programmable read-only memory (flash EEPROM). More particularly, this invention relates two-transistor flash EEPROM cells and arrays. Even more particularly this invention relates to methods and means to read, program, and erase digital data from a two-transistor flash EEPROM cell to improve endurance of the flash EEPROM cell.
2. Description of Related Art
The structure and application of the flash EEPROM is well known in the art and illustrated in “Technical Comparison of Floating Gate Reprogrammable Nonvolatile Memories,” (SST White Paper) staff, Silicon Storage Technology, Inc., November 2001 Technical Paper, found May 7, 2002 www.sst.com. The Flash EEPROM provides the density advantages of an erasable programmable read-only memory (EPROM) that employs ultra-violet light to eliminate the programming with the speed of a standard EEPROM.
FIG. 1
a
illustrates a cross-sectional view of a stacked gate flash EEPROM cell of the prior art. The stacked gate flash EEPROM cell is formed within a p-type substrate
10
. An n+ drain region
12
and an n+ source region
14
are formed within the p-type substrate
10
.
A relatively thin gate dielectric
16
is deposited on the surface of the p-type substrate
10
. The thin gate dielectric
16
is also referred to as a tunneling oxide. A poly-crystalline silicon floating gate
18
is formed on the surface of the gate dielectric
16
above the channel region
20
between the drain region
12
and source region
14
. An interpoly dielectric layer
22
is placed on the floating gate
18
to separate the floating gate
18
from a second layer of poly-crystalline silicon that forms a control gate
24
.
The source region
14
is connected to a source voltage generator through the source line
30
. The control gate
28
is connected through the word line
28
to the word line voltage generator. And the drain region
12
is connected through the bit line
24
to the bit line voltage generator.
According to conventional operation, the flash EEPROM cell is programmed by setting the word line voltage generator to a relatively high voltage (on the order of 10V). The bit line voltage generator is set to a moderately high voltage (on the order of 5V), while the source line voltage generator is set to the ground reference potential (0V).
With the voltages as described above, hot electrons will be produced in the channel
20
near the drain region
12
. These hot electrons will have sufficient energy to be accelerated across the gate dielectric
16
and trapped on the floating gate
18
. The trapped hot electrons will cause the threshold voltage of the field effect transistor (FET) that is formed by the flash EEPROM cell to be increased by three to five volts. This change in threshold voltage by the trapped hot electrons causes the cell to be programmed.
To erase the flash EEPROM cell a moderately high positive voltage (on the order of 5V) is generated by the source line voltage generator. Concurrently, the word line voltage generator is set to a relatively large negative voltage (on the order of −10V). The substrate
10
is set to the ground reference potential. The bit line voltage generator is usually disconnected from the bit line
26
to allow the drain region
12
to float. Under these conditions there is a large electric field developed across the tunneling oxide
16
in the source region
14
. This field causes the electrons trapped in the floating gate
18
to flow to portion of the floating gate
18
that overlaps the source region
16
. The electrons are then extracted to the source region
14
by the Fowler-Nordheim tunneling.
The flash EEPROM functions based on the electronic charge stored on the floating gate
18
sets the memory transistor to a logical “1” or “0”. Depending on whether the memory structure is an enhancement or depletion transistor when the floating gate is neutral or contains electrons (negative charge), the memory cell will or will not conduct during read. When the floating gate
18
is neutral or has an absence of negative charge, the memory cell will conduct during read. The conducting or nonconducting state is output as the appropriate logical level. In the memory cell as shown the word line voltage generator and the control gate
28
is set to the voltage level of the power supply voltage source. The substrate
10
and the source line voltage generator and thus the source
14
are set to the level of the ground reference voltage. The bit line voltage generator and the drain
12
are set to a small voltage level sufficient to cause a small current to conduct in the bit line
26
. The small current is detected by a sense amplifier connected to the bit line
26
to detect the presence or absence of the electronic charge and therefore the digital data stored on the flash EEPROM cell. If the floating gate
18
has an electronic charge, the threshold voltage of the memory cell increases and the memory cell does not conduct at the voltage level of the power supply voltage source and the sense amplifier detects a logical “1.” Alternately, if there is no electronic charge present on the floating gate
18
, the memory cell turns on and the sense amplifier detects a logical “0.”
As further described in the SST White Paper and illustrated in U.S. Pat. Nos. 6,314,022 (Kawata, et al.), 6,265,266 (Dejenfelt, et al.), 6,212,102 (Georgakos, et al.), 5,912,842 (Chang, et al.), and 5,612,913 (Cappelletti, et al.) a two-transistor thin oxide cell has a select transistor added to the cell to further control the read, program, and erase of the flash EEPROM cell. Refer now to
FIG. 1
b
for an illustration) of a two-transistor thin oxide flash EEPROM cell with a select transistor of the prior art. The source of the select transistor is formed of the drain
12
of the memory cell. The drain of the select transistor is formed of the n+ region
32
. A layer of poly-crystalline silicon is placed over the thin oxide layer
16
between the source region
12
and the drain region
32
of the select transistor to form the control gate
34
of the select transistor. The control gate
34
is connected to a gate select line
36
. The gate select line allows the control of the application of the higher voltages to the memory cell when the flash EEPROM cell is being selected or not selected and thus helps mitigate the effects of the higher voltages on the memory cell.
A split gate flash EEPROM cells, as shown in
FIG. 1
c
, is described in the SST White Paper and illustrated in U.S. Pat. Nos. 6,212,100 (Choi), 6,103,576 (Deustcher, et al.), 6,034,892 (Choi), 5,859,454 (Choi, et al.), 5,852,577 (Kianian, et al.). The split gate flash EEPROM cell is formed within a p-type substrate
50
. An n+ drain region
52
and an n+ source region
54
are formed within the p-type substrate
50
.
A relatively thin gate dielectric
56
is deposited on the surface of the p-type substrate
50
. A poly-crystalline silicon floating gate
58
is formed on the surface of the gate dielectric
56
above the channel region
60
between the drain region
52
and source region
54
. An interpoly dielectric layer
62
is placed on the floating gate
58
to separate the floating gate
58
from a second layer of poly-crystalline silicon that forms a control gate
64
. A field enhancing tunneling injector
63
is formed on the floating gate
58
to assist to in erasure of the split gate EEPROM cell. The control gate
64
is formed in stepped fashion having a portion resting on the interpoly dielectric
62
above the floating gate
58
and another portion resting directly upon the gate dielectric
56
essentially forming a two-transistor memory cell as shown in FIG.
2
. In
FIG. 2
, the split gate transistor is represented by the select transistor Txs
72
and the memory transistor Txm
74
. The portion of the split gate EEPROM cell representing the select transistor
72
is the region
Ackerman Stephen B.
Knowles Billy
Phan Trong
Saile George O.
Taiwan Semiconductor Manufacturing Company
LandOfFree
Two-transistor flash cell for large endurance application does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Two-transistor flash cell for large endurance application, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Two-transistor flash cell for large endurance application will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3338663