Two transistor EEPROM cell using P-well for tunneling across a c

Details Two transistor EEPROM cell using P-well for tunneling across a c Two transistor EEPROM cell using P-well for tunneling across a c

1999-01-27

1999-12-07

Nelms, David

Static information storage and retrieval

Floating gate

Particular connection

36518528, 36518529, G11C 1134

Patent

active

059994495

ABSTRACT:
A two transistor EEPROM cell is described that is programmed and erased by electron tunneling across a tunneling channel in a P-well. The EEPROM cell has two transistors formed in a semiconductor substrate. The two transistors are a tunneling transistor (NMOS) and a read transistor (NMOS). Electron tunneling occurs to program and erase the EEPROM cell through a tunnel oxide layer by electron tunneling across an entire portion of a tunneling channel upon incurrence of a sufficient voltage potential between a floating gate and the tunnel channel

REFERENCES:
patent: 4924278 (1990-05-01), Logie
patent: 5457652 (1995-10-01), Brahmbhatt
patent: 5487033 (1996-01-01), Keeney et al.
patent: 5615152 (1997-03-01), Bergemont

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