Two step variable length delay circuit

Details Two step variable length delay circuit Two step variable length delay circuit

2002-01-31

2003-11-18

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S284000, C327S298000

Reexamination Certificate

active

06650160

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a two step variable length delay circuit, in particular, which is used for a delay-locked loop (DLL) in a clock generating circuit of an information processing apparatus and in a timing generating circuit of a communication processing apparatus.
DESCRIPTION OF THE RELATED ART
As a first conventional example, a technical report, “A Semidigital Dual Delay-Locked Loop” written by S. Sidiropoulos et al., has been reported in IEEE Journal of Solid-State Circuits, vol. 32, pp. 1683-1692, November 1997. And as a second conventional example, Japanese Patent Application Laid-Open No. HEI 11-261408 discloses “Phase Interpolator, Timing Signal Generating Circuit, and Semiconductor Integrated Circuit and Semiconductor Integrated Circuit System Applied This Timing Signal Generating Circuit.” In these conventional examples, a variable length delay circuit is realized by an analog mixer circuit that mixes currents of two signals whose phases are different each other, however, it is difficult to realize its required specifications due to the dispersion of the circuits. Therefore, a variable length delay circuit, in which its easy designing and operation stability are secured by using digital circuits, has been required.
As a third conventional example, a technical report, “A Portable Digital DLL Architecture for CMOS Interface Circuits” written by Bruno W. Garlepp et al., has been reported in 1998 Symposium on VLSI Circuits Digest of Technical Papers, pp. 214-215. In this conventional example, in order to meet the request mentioned above, not only a controlling circuit but also delay elements are digitized.
FIG. 1
is a circuit diagram showing a two step variable length delay circuit including interpolators at the third conventional example. Referring to
FIG. 1
, the two step variable length delay circuit at the third conventional example is explained.
The two step variable length delay circuit at the third conventional example provides inputs In
1
and In
2
, outputs a to c and e to i, buffers (inverters) B
100
to B
103
, B
121
to B
123
, B
123
i
, B
200
to B
203
, and B
213
i
, and interpolators ip
120
, ip
121
, and ip
122
.
The interpolator ip
120
provides buffers B
120
and B
210
, the interpolator ip
121
provides buffers B
120
i
and B
121
i
, and the interpolator ip
122
provides buffers B
210
i
and B
211
i.
In this, an output from the inverter B
100
, to which the input In
1
is inputted, is amplified by the buffer B
101
and the output a is outputted, and an output from the inverter B
200
, to which the input In
2
is inputted, is amplified by the buffer B
201
and the output c is outputted. The interpolator ip
120
mixes currents of the outputs from the buffers B
120
and B
210
by connecting them, and the output from the interpolator ip
120
is amplified at the buffer B
121
and the output b is outputted. And the phase of the output b becomes the middle phase of the outputs a and c in this digital circuit of the two step variable length delay circuit at the third conventional example.
Further, the output a from the buffer B
101
is inputted to the inverter B
102
, and the buffer B
103
amplifies the output from the inverter B
102
. The output b from the buffer B
121
is inputted to the inverter B
122
, and the buffer B
123
amplifies the output from the inverter B
122
. The interpolator ip
121
outputs a signal by connecting the output from the B
120
i
, to which the output a is inputted, and the output from the B
121
i
, to which the output b is inputted, and the buffer B
123
i
amplifies the output from the interpolator ip
121
. The interpolator ip
122
outputs a signal by connecting the output from the B
210
i
, to which the output b is inputted, and the output from the B
211
i
, to which the output c is inputted, and the buffer B
213
i
amplifies the output from the interpolator ip
122
. The output c from the buffer B
201
is inputted to the inverter B
202
, and the buffer B
203
amplifies the output from the inverter B
202
. With this structure, fine time intervals are obtained.
At the third conventional example, as mentioned above, three interpolators are used and the eight outputs are obtained by dividing the input phases into eight. In this, actually, nine outputs are obtained, but the ninth output is not outputted, because the ninth output is equal to the first output at the next output combination.
As a fourth conventional example, Japanese Patent Application Laid-Open No. 2000-163961 discloses “Synchronous Type Semiconductor IC.” In this application, an internal clock signal being synchronized with an external clock signal is generated by applying a fine adjustment to phases, after a coarse adjustment was applied to the phases. With this, generating a glitch caused by the change of the input signal is prevented.
As a fifth conventional example, Japanese Patent Application Laid-Open No. 2000-195166 discloses “Delay Time Control Circuit.” In this application, pulse signals delayed by a designated delay time are counted by using a delay circuit, and pulse signals having a suitable delay time are generated, even when the delay time of a unit circuit is changed.
As a sixth conventional example, Japanese Patent Application Laid-Open No. 2000-252802 discloses “Clock Cycle Detecting Circuit.” In this application, an operating range of the phase adjustment is widened by applying the coarse adjustment beforehand.
As a seventh conventional example, Japanese Patent Application Laid-Open No. 2000-298532 discloses “Timing Control Circuit.” In this application, the timing control circuit provides a coarse timing control circuit that coarsely adjusts the phase difference between an input clock signal and an output clock signal, and a fine timing control circuit that finely adjusts the phase difference in case that the delay time is change caused by like a temperature rise.
And as an eighth conventional example, Japanese Patent Application Laid-Open No. HEI 6-204792 discloses “Delay Circuit.” In this application, the delay circuit provides a coarse adjusting section and a fine adjusting section, and adjusts the amount of delay by using a wide variable range and a fine minimum step.
At the third conventional example shown in
FIG. 1
, in order to form a middle phase at an interpolator, the sizes (on resistance values) of transistors are decided in the following. That is, the size of the transistors of the two step inverters B
100
and B
101
, which generate the outputs a, is 10, and also the size of the transistors of the two step inverters B
200
and B
201
, which generate the outputs c, is 10. And the size of transistor of the inverter B
120
connecting to the input In
1
whose phase is lead is set to be 6, and the size of transistor of the inverter B
210
connecting to the input In
2
whose phase is lag is set to be 4. And by connecting the outputs from the B
120
and B
210
, the output b having the middle phase between the outputs a and c is obtained by mixing through the inverter B
121
formed by the size of transistor being 10.
At this time, a phase lead signal in the two signals is inputted to the input In
1
, and even when the inverter B
120
, whose output is connected to the output of the inverter B
210
, changes, the inverter B
210
, to which a phase lag signal is inputted, stays unchanged. And since both a p channel transistor of the B
120
and an n channel transistor of the B
210
become “on”, the output becomes a voltage divided value by the on resistance of the both transistors. Consequently, the phase lead input signal is delayed more than the value outputting from the two step inverters B
100
and B
101
, and when the phase lag signal is inputted to the In
2
and the B
210
changes, the phase lead signal is changed immediately. Therefore, the phase lead signal changes faster than that the phase lag signal is outputted from the two step inverters B
200
and B
201
. With this, a middle phase signal output can be obtained.
However, when the phase lead signal is inputted to the input In
1
, which is connecte

Affiliated with

Also associated with

Rating

Two step variable length delay circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Two step variable length delay circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Two step variable length delay circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3159283