Two-step sinter method utilized in conjunction with memory cell

Details Two-step sinter method utilized in conjunction with memory cell Two-step sinter method utilized in conjunction with memory cell

1995-05-26

1996-05-07

Thomas, Tom

Fishing, trapping, and vermin destroying

437 8, 437 52, 437923, H01L 21324

Patent

active

055146287

ABSTRACT:
A process is disclosed herein for increasing yield in a semiconductor circuity having redundant circuitry for replacing defective normal circuitry in the semiconductor integrated circuit. In the first step, an insufficient sinter operation (50) is carried out in a hydrogen atmosphere at a temperature of less than 350.degree. C. At this temperature, no significant change will be seen in the interface trap density. Thereafter, the integrated circuit is tested (54,56) and the defective normal circuitry then is replaced (58) with the redundant circuitry. The integrated circuit is then subjected to a sufficient sinter operation (64) which is an operation wherein the substrate is disposed at a temperature between 350.degree. C.-500.degree. C. for more than 30 minutes. This sufficient sinter operation is performed in a hydrogen atmosphere, allowing dangling bonds at the interface to be terminated with hydrogen. Preferable, the optimal temperature for the sufficient sinter is approximately 400.degree. C. The integrated circuit is then subjected to a reliability and burn-in procedure.

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E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology, 1982, pp. 285-295, 774-791, 820-825.

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