Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-09-20
2001-04-03
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S695000, C438S787000
Reexamination Certificate
active
06211040
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating silicon structures, and more particularly, to a process for depositing silicon dioxide between features in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
As device feature size and gate oxide thickness are further scaled down, it becomes more difficult to form interlayer dielectrics. One of the techniques used to form an isolation oxide layer in integrated circuits with very narrowly spaced features, such as metal lines, is through the use of high density plasma, chemical vapor deposition (HDP CVD) processing.
In HDP CVD, a traditional CVD process for depositing silicon dioxide is combined with a simultaneous sputtering process. As the silicon dioxide layer is deposited, it is also sputtered, or etched by the high-density plasma. By combining both a deposition and an etching action in the same process, a very dense and high quality silicon dioxide layer may be formed. In addition, since the etching component can be anisotropically controlled, that is, can etch in specific directions, the HDP CVD offers a significant advantage for deposition of silicon dioxide inside gaps or trenches. The etching component can reduce the deposition rate on vertical sidewalls such that the gap can be filled from the bottom up without the top of the gap closing or pinching off. This prevents the formation of voids or keyholes in the silicon dioxide layer.
Referring now to
FIG. 1
, an insulating layer
14
is shown formed overlying a semiconductor substrate
10
. A pair of metal traces
18
overlies the insulating layer
14
. In this situation, it is desirable to form an oxide layer overlying the metal traces
18
and insulating the gap between metal traces
18
. In addition, the space between the metal traces is very narrow, at between about 0.2 microns and 0.3 microns. The height of the metal traces is between about 0.55 microns and 1.0 microns such that the aspect ratio of the gap is about 3.
A HDP CVD process is used as typical in the art to form the silicon dioxide layer
22
. The HDP CVD process would typically use a gas mixture of silane (SiH
4
), oxygen, and argon. The silane and oxygen components provide the source species for the deposition of the silicon dioxide. The argon gas is ionized to form the high-density plasma to etch the silicon dioxide layer
22
as this layer is deposited.
As the silicon dioxide layer
22
is deposited, the sputtering reaction also removes some of the material. As shown, the greatest sputter rate is at the corner of the gap. Here, the silicon dioxide layer
22
overlaps the contour of the metal trace
18
. The combined deposition and etching reaction creates the angled profile
26
of approximately 45 degrees. This angled profile
26
aids the deposition process by preventing the silicon dioxide layer
22
from closing or pinching off before the gap has been filled completely from below.
The etching rate of the reaction is directly controlled by the partial pressure of the argon gas component of the gas mixture and by the high frequency radio frequency (HFRF) sputter energy. The argon gas is typically flowed at a rate of between about 350 sccm and 400 sccm and constitutes approximately between about 64% and 67% of the gas pressure in the reaction. The HFRF energy is typically in the range of between about 2,500 watts and 3,000 watts. By carefully setting the deposition rate via the silane and oxygen gas flows and the etching rate via the argon gas flow and HFRF energy, an optimal etch to deposition ratio can be established to guarantee gap fills.
This process approach has its limitations, however. If the etching component of the reaction is too low, the silicon dioxide layer
22
pinches off the gap before it has completely filled from the bottom. As a consequence, a keyhole, or void,
30
has formed. This void causes serious reliability problems because of the potential for trapped contamination.
Referring now to
FIG. 2
, a second possible problem is shown. Here, the etching component is too high. As a consequence, corner clipping
34
occurs. In corner clipping, the plasma etches into the metal traces
18
. This problem also represents a potential reliability issue.
As the aspect ratio of the gaps becomes larger, it is not possible to select a single operating point for the HDP CVD process that will both eliminate the corner clipping
34
and prevent the formation of voids
30
. In addition, the use of argon plasma poses the additional risk of plasma induced damage (PID) to underlying gate oxide layers. PID occurs because of charging of the semiconductor wafer that occurs due to the plasma. If this charge is sufficiently large, very thin gate oxides can be damaged due to electrical overstress.
Several prior art approaches disclose methods to form silicon dioxide layers, and specifically, to fill gaps between features in the fabrication of integrated circuits. U.S. Pat. No. 5,872,058 to Van Cleemput et al discloses a process to fill gaps with oxide using HDP and CVD. A gas mixture comprising silicon containing, oxygen containing and inert gases is used. The inert gas component of this mixture comprises not more than 13% of the total gas mixture. An electron cyclotron resonance (ECR) process is used with high microwave power for gas dissociation to form the plasma. A single RF frequency is used to drive the argon ion bombardment. Argon is eliminated during the formation of the protective layer. Multiple steps of PE-CVD and HDP are used. U.S. Pat. No. 5,814,564 to Yao et al teaches a process to gap fill with oxide and then to planarize with a spin-on glass layer. A six step etch back process is used in the final planarization. U.S. Pat. No. 5,807,785 to Ravi discloses a process for silicon dioxide gap fill where a plasma enhanced CVD process using TEOS forms a first barrier layer overlying metal traces. A subatmospheric CVD (SACVD) process using TEOS forms the gap filling layer. U.S. Pat. No. 5,679,606 to Wang et al teaches a process to fabricate gap fills of oxide using two steps. In the first step, a protective layer is deposited by HDP CVD without any argon gas flow or sputter rf energy. In the second step, the gap fill layer is deposited using HDP CVD with argon and sputter rf energy. U.S. Pat. No. 5,494,854 to Jain discloses a process for gap filling and planarization. First, a seed layer is deposited using HDP with no sputter rf power. Second, a gap filling layer of approximately equal thickness is deposited using HDP with sputter rf power. A polishing layer and planarization step complete the process.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of depositing silicon dioxide between features in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to deposit silicon dioxide between features using a two-step, low argon pressure, high-density plasma, chemical vapor deposition process that prevents the formation of voids.
A yet further object of the present invention is to use a two-step, low argon pressure, high-density plasma, chemical vapor deposition process that prevents corner clipping or etching of features.
In accordance with the objects of this invention, a new method of depositing silicon dioxide between features has been achieved. Features, such as conductive traces, are provided overlying a semiconductor substrate where the spaces between the features form gaps. A silicon dioxide liner layer is deposited overlying the features and lining the gaps, yet leaving the gaps open. The step of depositing the silicon dioxide liner layer is by high density plasma, chemical vapor deposition (HDP CVD) using a gas mixture comprising silane, oxygen, and argon. The argon gas pressure, chamber pressure, and the sputter rf energy are kept low. A silicon dioxide gap filling layer is deposited overlying the silicon dioxide liner layer to fill the gaps, and the integrated circuit device is compl
Lin Charles
Lin Quah Ya
Liu Huang
Sudijono John
Chartered Semiconductor Manufacturing Ltd.
Nguyen Tuan H.
Pike Rosemary L. S.
Saile George O.
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