Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-11-28
2003-07-15
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S424000, C156S345420, C216S088000, C216S089000, C451S041000, C451S285000
Reexamination Certificate
active
06593240
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to a method for planarization of semiconductor wafers in a two step polish process.
2. Description of the Related Art
Semiconductor devices are fabricated by processing layers of materials deposited on a surface of a substrate. One such process includes planarizing a top surface to remove, flatten or smooth the top surface. Planarization techniques are not always uniform across a top surface of a wafer, however, and often depend on the type and density of devices already formed below the layer to be planarized. A final step in the fabrication of isolation regions for semiconductor devices typically includes a chemical-mechanical polishing (CMP) process. The CMP process is employed to planarize and/or remove dielectric material, such as oxide for the isolations regions from a top surface of the wafer.
Referring to
FIG. 1
, during CMP, a wafer
10
is held in a carrier
12
, device side facing down. The device side is applied to a pad
14
, which is affixed to a table
16
. The table
16
and carrier
12
spin, force is applied through the carrier
12
, and slurry or chemical
18
is dispensed in the pad
14
.
Conventionally, oxide CMP employs a very hard urethane pad stacked on a soft felt pad. As shown in
FIG. 2
, a hard pad
20
is stacked on a soft pad
22
. The composite of the two pads tends to deform, reducing planarization effectiveness, as illustrated in FIG.
2
. The result of the pad deformation is reduced planarization. To compensate for the reduced planarization, a mask and etch step is performed. In addition, typically, after planarization is achieved, additional polishing is necessary to achieve a remaining oxide target thickness (i.e., reduce the oxide thickness). To provide proper planarization and target thicknesses, a very uniform, well-controlled process is required.
To attempt to make the planarization process more uniform, preprocessing steps may be employed. In one case, a mask process and an etching process are employed to remove material in selected areas to provide a more uniform layer to be planarized. For example, one method for forming isolation regions includes a deposition of an oxide for a void free fill, a masking and etch step to assist planarization by reducing the oxide over large features and a film removal and planarization by means of a chemical mechanical polish.
One problem with a mask and etch process is that the mask process is typically very expensive. An etch mask must be developed which includes regions which need to be etched and regions which are not be etched. The masking steps, lithographic steps and the etching steps require process time and materials. This makes the preprocessing needed to assist planarization less attractive, especially in sub 0.25 micron technology. However, the elimination of the masking step is generally considered not possible when employing high density plasma deposited films with current chemical-mechanical polishing (CMP) consumables because improved planarization is at the expense of global uniformity.
Therefore, a need exists for a method of depositing and planarizing a dielectric layer with improved global uniformity without the need for preprocessing, such as, for example, masking and etching the dielectric layer before planarization. A further need exists for increased throughput for polishing processes.
SUMMARY OF THE INVENTION
A method for polishing a semiconductor wafer, in accordance with the present invention, includes providing a semiconductor wafer having topographical features and forming a dielectric layer on the semiconductor wafer to fill portions between the features. The dielectric layer is planarized across the entire semiconductor wafer for a first portion of a polishing process. The dielectric layer is polished for bulk removal of the dielectric layer for a remaining portion of the polishing process.
Another method for polishing a semiconductor wafer, includes the steps of providing a semiconductor wafer having topographical features, forming a dielectric layer on the semiconductor wafer to fill portions between the features, providing a first polishing substance on a planarization polishing pad, planarizing the dielectric layer with the first polishing substance and the planarization polishing pad for a first portion of a polishing process, providing a second polishing substance on a bulk removal polishing pad, and polishing the dielectric layer with the second polishing substance and the bulk removal polishing pad for bulk removal of the dielectric layer for a remaining portion of the polishing process.
Yet another method for polishing a semiconductor wafer, includes the steps of providing a semiconductor wafer having topographical features, forming a dielectric layer on the semiconductor wafer to fill portions between the features, providing a first platen of a polishing tool with a first slurry on a single non-stacked polishing pad, planarizing the dielectric layer with the first slurry and the single non-stacked polishing pad for a first portion of a polishing process, providing a second platen on the polishing tool with a second slurry on a stacked polishing pad, transferring the wafer to the second platen, and polishing the dielectric layer with the second slurry and the stacked polishing pad for bulk removal of the dielectric layer for a remaining portion of the polishing process.
In other methods, the step of planarizing may include employing a single non-stacked polishing pad, which may include, for example, urethane or a fixed abrasive pad. The step of polishing the dielectric layer may include employing a stacked polishing pad. The stacked polishing pad may include a first pad for contacting the wafer and a second pad for supporting the first pad. The second pad may be softer than the first pad to improve polishing uniformity, surface finishing, and defectivity. The step of polishing the dielectric layer may include employing a single felt pad. The step of polishing may include the step of polishing with precipitated silica particle slurry. The step of planarizing may include the step of polishing with fumed silica slurry. The step of planarizing may include the step of polishing with a fixed abrasive pad and a chemical for activating the polishing of the fixed abrasive pad. The steps of planarizing and polishing may be performed on different platens of a same tool. The first portion is preferably about 50% of a total polishing time for the polishing process.
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Infineon Technologies North America Corp
Niebling John F.
Pompey Ron
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