Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
1999-05-19
2001-07-03
Picardat, Kevin M. (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S381000, C438S584000, C438S796000
Reexamination Certificate
active
06255185
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor processing, and in particular to a method of fabricating a polysilicon resistor wherein two different annealing steps are employed to control the resistance and/or tolerance of the resistor. The two different annealing steps may be performed any time during the manufacturing of the integrated circuit, i.e. during source/drain activation, bipolar emitter activation, silicide formation or growing a dielectric film. Specifically, it has been found that by applying a second anneal after a high temperature anneal, the resulting resistance of a polysilicon resistor can be set to a specified value and the resistor tolerance across wafer and from lot to lot can be improved significantly. Moreover, by adjusting the temperature of the second anneal, it is possible to vary the resistance of the polysilicon resistor.
BACKGROUND OF THE INVENTION
Semiconductor structures and integrated circuits are manufactured using a wide variety of well known techniques. In the manufacturing of semiconductor devices or integrated circuits, active/passive components are formed on a semiconducting substrate such as silicon, and then interconnected in a desired manner.
Resistors are typically formed in such structures using one of two well known techniques. In the first technique, regions of the semiconductor substrate are doped with n- or p-type dopants. This provides conductive regions in the substrate having a desired resistivity. By forming ohmic contacts to a pair of spaced-apart locations in such regions, a diffused region is provided. Such resistors are referred to in the art as diffused resistors.
In the second technique, an insulator layer, i.e. dielectric layer, is formed on the surface of a semiconductor substrate. Next, a layer of polysilicon is formed on the insulator layer. The polysilicon film is either doped in-situ or it is doped with a n- or p-type dopant after deposition of the same. Again, the dopants form a conductive region having a desired resistivity. To complete the resistor, ohmic connections are formed on a pair of spaced-apart regions on the polysilicon layer. These resistors are referred to in the art as polysilicon resistors.
Compared with diffused resistors, polysilicon resistors offer a significant advantage in that they do not consume any area in the semiconductor substrate itself. Thus, the substrate remains available for the fabrication of active components, while the resistor interconnections can be made directly above the active components themselves. Moreover, since the resistor is separated the semiconductor substrate by an insulating layer, the polysilicon resistors have a substantially lower capacitance with the substrate than their diffused counterparts.
One major drawback of such polysilicon resistors is that the polysilicon resistors are sensitive to low temperature variation in excess of about 500° to about 600° C. The exact temperature sensitivity depends on the dopant species found in the polysilicon layer as well as the composition, i.e. grain boundaries and grain size, of the polysilicon itself. Therefore, if the temperature of the back end of the line (BEOL) or later front end of the line (FEOL) process changes, the resistance of the polysilicon resistor will often vary to a value below the targeted resistance. For example, in the development of N+ type polysilicon resistors for BiCMOS, the resistance of the polysilicon resistor dropped by approximately 20% due to changes in the low temperature processing in the range described above.
In view of the above mentioned drawback with prior art polysilicon resistors, there is a continued need for developing new and improved methods which can substantially eliminate the variance in resistance caused by low temperature thermal processing that may occur during subsequent BEOL or FEOL processing. There is also a need for developing a processing method which is capable of providing a controllable resistance to a polysilicon resistor that has a high degree of tolerance for low BEOL and FEOL processing temperatures.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of manufacturing a polysilicon resistor which substantially eliminates the variance in resistance caused by low temperature BEOL and FEOL processing.
Another object of the present invention is to develop a method which can be easily implemented after any high temperature (about 800° C. or higher) device activation anneal step typically used in manufacturing the integrated circuit.
It is noted that the temperature range for the high temperature device activation anneal employed in the present invention depends on the dopant type as well as the polysilicon composition. Thus, the lower temperature limit of the high temperature device activation anneal may fluctuate about ±20° C. The term “device activation” is used herein to denote any anneal whose function it is to provide an active region in and/or on an integrated circuit. That is, any anneal capable of forming activated source/drain diffusion regions in a semiconductor substrate, an anneal capable of forming an activated bipolar emitter region, or an anneal capable of forming a silicide or dielectric region on a structure.
A further object of the present invention is to provide a method which can render a predetermined resistance value to a polysilicon resistor which is either higher or lower that which can be obtained by merely employing the high temperature device activation anneal.
A still further object of the present invention is to provide a method which effects only the resistance value of the polysilicon resistor, while causing little or no changes to other parametrics of the integrated circuit.
These and other objects and advantages can be obtained in the present invention by employing a second anneal step which follows a high temperature device activation anneal step. The second annealing step can be carried out at a temperature lower than about 800° C. This embodiment causes deactivation of the dopants within the polysilicon layer and a subsequent increase in the resistance of the polysilicon resistor.
In another embodiment of the present invention, the second annealing step may be carried out at a temperature higher than about 800° C. In this embodiment of the present invention, the second annealing step causes activation of the dopant atoms within the polysilicon layer and a subsequent decrease in the resistance of the polysilicon resistor.
Specifically, the first embodiment of the present invention comprises the steps of:
(a) providing a polysilicon resistor structure, said polysilicon resistor structure comprising a semiconductor substrate, a dielectric layer formed on said semiconductor substrate, and a doped polysilicon layer formed on said dielectric layer;
(b) forming device regions on and/or in the structure provided in (a);
(c) conducting a high temperature device activation anneal on the structure provided in (b), said high temperature device activation anneal being carried out at a temperature of about 800° C. or above; and
(d) conducting a second anneal, after said high temperature device activation anneal, at a temperature less than about 800° C. so as to cause an increase in resistance of said polysilicon resistor.
In the second embodiment described above, the inventive method comprises the steps of:
(a) providing a polysilicon resistor structure, said polysilicon resistor structure comprising a semiconductor substrate, a dielectric layer formed on said semiconductor substrate, and a doped polysilicon layer formed on said dielectric layer;
(b) forming device regions on and/or in the structure provided in (a);
(c) conducting a high temperature device activation anneal on said structure provided in (b), said high temperature device activation anneal being carried out at a temperature of about 800° C. or above; and
(d) conducting a second annealing step, after said high temperature device activation anneal, at a temperature higher than about 800° C. so as to cause a decre
Coolbaugh Douglas Duane
Miller Glenn Robert
Ratenberg Sophia Maumovna
Collins D. M.
International Business Machines - Corporation
Picardat Kevin M.
Sabo William D.
Scully Scott Murphy & Presser
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