Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-08-27
2001-05-08
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C365S189110
Reexamination Certificate
active
06229381
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to integrated circuits, and, more particularly, to a two-stage voltage pump for providing an internal voltage supply at a higher voltage magnitude than an external power supply voltage.
2. Description of the Related Art
System designs are routinely constrained by a limited number of readily available power supply voltages (V
cc
). For example, consider a portable computer system powered by a conventional battery having a limited power supply voltage. For proper operation, different components of the system, such as display, processor, and memory components employ diverse technologies that require power to be supplied at various operating voltages. Components often require operating voltages of a greater magnitude than the power supply voltage and, in other cases, a voltage of reverse polarity. The design of a system, therefore, includes power conversion circuitry to efficiently develop the required operating voltages. One such power conversion circuit is known as a voltage pump. The demand for highly-efficient and reliable voltage pump circuits has increased with the increasing number of applications utilizing battery powered systems, such as notebook computers, portable telephones, security devices, battery-backed data storage devices, remote controls, instrumentation, and patient monitors, to name a few.
Inefficiencies in conventional voltage pumps lead to reduced system capability and lower system performance in both battery and non-battery operated systems. Inefficiency can adversely affect system capabilities, e.g., limited battery life, excess heat generation, and high operating costs. Samples of lower system performance include low speed operation, excessive operating delays, loss of data, limited communication range, and inability to operate over wide variations in ambient conditions including ambient light level and temperature.
In addition to constraints on the number of power supply voltages available for system design, there is an increasing demand for reducing magnitudes of the power supply voltages. Current voltage pump circuits have difficulty providing sufficiently high output voltages as the supply voltage approaches two volts.
An exemplary prior art voltage pump circuit
10
is shown in FIG.
1
. Only one of the two complimentary phases is shown. The other phase is symmetrical to the phase shown in the voltage pump circuit
10
. Typically, an oscillator signal is used to generate non-overlapping complimentary enable signals for alternately firing each phase. The voltage pump circuit
10
includes capacitors
12
,
14
. During a charging phase, the output signals of inverters
16
,
18
are held at a low voltage level. The charging phase of one phase corresponds to the firing phase of the other phase. During the charging phase, control signals C
1
, C
2
enable the gates of transistors
20
,
22
, coupling the capacitors
12
,
14
to a voltage supply
24
(Vdd) and charging them to a voltage of Vdd. The control signals C
1
, C
2
are generated from the firing signals of the other phase.
During the firing phase, the transistors
20
,
22
are disabled, and the inverters
16
,
18
are driven to a high output voltage (ie., booted), thus raising the voltage on the capacitors
12
,
14
to ~2*Vdd. The inverter
18
is enabled slightly after the inverter
16
to allow the capacitor
12
to fully boot. After the inverter
18
is enabled, the voltage present on the capacitor
14
enables a pass gate
24
, which connects the capacitor
12
to the output voltage line, Vccp, and the capacitor delivers its charge. Clamping transistors
26
,
28
keep the voltage on the capacitors
12
,
14
from falling below a threshold drop, Vt, under Vdd during the charging phase to increase circuit efficiency. A filtering capacitor
30
is coupled to the Vccp output terminal. The voltage pump circuit
10
has an unregulated output voltage of about 3.5V (Vccp) with a 2V supply voltage (Vdd). This output voltage is insufficient for some integrated circuit applications.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a voltage pump circuit including a voltage output line, first and second stages, and timing control logic. The first stage includes a first capacitor and a first switching device coupled to the first capacitor. The second stage includes a second capacitor coupled to the first switching device and a second switching device coupled between the second capacitor and the voltage output line. The timing control logic is adapted to charge the first capacitor, boot the first capacitor, enable the first switching device to transfer the charge in the first capacitor to the second capacitor, boot the second capacitor, and enable the second switching device to transfer the charge in the second capacitor to the voltage output line.
Another aspect of the present invention is seen in a method for providing an output voltage at a level higher than an input voltage. A first capacitor in a first stage of a voltage pump circuit is charged to the input voltage. The first capacitor is booted with the input voltage. The charge in the first capacitor is transferred to a second capacitor in a second stage of the voltage pump circuit. The second capacitor is booted with the input voltage. The charge in the second capacitor is transferred to a voltage output line.
REFERENCES:
patent: 5524266 (1996-06-01), Tedrow et al.
patent: 5644534 (1997-07-01), Soejima
patent: 5698972 (1997-12-01), Keeth
patent: 5880622 (1999-03-01), Evertt et al.
patent: 5939935 (1999-08-01), Merritt
patent: 6037622 (2000-03-01), Lin et al.
A schematic representation of a circuit included at p. 15 of Fujitsu 64 Meg Sync DRAM.
Cunningham Terry D.
Micro)n Technology, Inc.
Tra Quan
Williams Morgan & Amerson P.C.
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