Two stage register for capturing asynchronous events and subsequ

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395550, 3642383, 3642396, 3642397, 3642716, 3642718, 364DIG1, G06F 300

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active

054506026

ABSTRACT:
An improved event catching read and reset register system responsive to event data signals from a data source and register select and register read and reset signals from a reading processor is provided. The system includes a generator for generating first and second control signals from the register select and register read signals. The read and reset register or registers simultaneously capture the event data and read out and reset the register in response to these control signals.

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Morris, "Computer Engineering Hardware Design", 1988, pp. 103-109 and 246-251.
Voorhees, "Foolproof Event-Catching Register Circuit", IBM Technical Disclosure Bulletin, vol. 32, No. 5A, Oct. 1989, pp. 214-216.
Pennec et al., "Set/Reset System with Slow Set and Fast Reset", IBM Technical Disclosure Bulletin, vol. 32, No. 6B, Nov. 1989, pp. 217-218.

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