Two stage push-pull output buffer circuit with control logic fee

Details Two stage push-pull output buffer circuit with control logic fee Two stage push-pull output buffer circuit with control logic fee

1991-03-11

1992-03-17

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307263, 307473, H03K 1716

Patent

active

050971492

ABSTRACT:
A low noise output buffer circuit that activates and deactivates the output by means of a two stage NAND and FET circuit. The two stages turn on sequentially but turn off simultaneously and minimizes the peak power supply current that normally appears during input and output switching operations.

REFERENCES:
patent: 4777389 (1988-10-01), Wu et al.
patent: 4785201 (1988-11-01), Martinez
patent: 4785203 (1988-11-01), Nakamura
patent: 4789796 (1988-12-01), Foss
patent: 4800298 (1989-01-01), Yu et al.
patent: 4818901 (1989-04-01), Young et al.
patent: 4820942 (1989-04-01), Chan
patent: 4855623 (1989-08-01), Flaherty
patent: 4918339 (1990-04-01), Shigeo et al.

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