Two-stage pipelined recycling analog-to-digital converter (ADC)

Details Two-stage pipelined recycling analog-to-digital converter (ADC) Two-stage pipelined recycling analog-to-digital converter (ADC)

1999-08-12

2001-02-27

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S156000, C341S163000

Reexamination Certificate

active

06195032

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to Analog-to-Digital converters (ADCs), and more particularly to multi-stage, pipelined recycling ADCs.
BACKGROUND OF THE INVENTION
Digital signal processing has been an enabling technology for high-speed telephony. Digital-Subscriber Lines (DSL) use highly-complex digital processing for line coding, data compression, and error correction. However, signals transmitted over the copper-pair telephone lines are analog signals. Conversion between the analog telephone signal and digital words is thus a critical piece of DSL systems.
Many kinds of Analog-to-Digital Converters (ADC's) have been used for a wide variety of applications. Flash ADC's compare analog signal voltages to multiple voltage levels in an instant to produce a multi-bit digital word that represents the analog voltage. Successive-approximation ADC's use a series of stages to convert an analog voltage to digital bits. Each stage compares an analog voltage to a reference voltage, producing one digital bit. In sub-ranging ADC's, each stage compares an analog voltage to several voltage levels, so that each stage produces several bits. Succeeding stages generate lower-significant digital bits than do earlier stages in the pipeline.
Algorithmic, re-circulating, or recycling ADC's use a loop to convert an analog voltage. The analog voltage is sampled and compared to produce a most-significant digital bit. Then the digital bit is converted back to analog and subtracted from the analog voltage to produce a residue voltage. The residue voltage is then multiplied by two and looped back to the comparator to generate the next digital bit. Thus the digital bits are generated over multiple cycles in the same comparator stage.
Many interesting variations of these basic ADC types have been disclosed. See U.S. Pat. No. 5,459,465 by Kagey, U.S. Pat. No. 5,302,869 by Hosotani et al., and U.S. Pat. No. 5,436,629 by Mangseldorf.
FIG. 1
shows a prior-art pipelined ADC. See “A 2.5-v, 12-b 5-Msample/s Pipelined CMOS ADC”, by Yu and Lee, IEEE Journal of Solid-State Circuits, Vol. 31, No. 12, December 1996, pp. 1854-61. Two stages
10
,
10
′ are shown of the pipeline. Each stage
10
,
10
′ converts its analog input to B digital bits. Sample-and-hold amplifier
12
receives the stage's analog input. ADC
14
receives the sampled analog voltage from amplifier
12
and converts it to B digital bits. These B digital bits are stored and also input to DAC
16
.
DAC
16
re-converts the B digital bits back to an analog voltage that is applied to subtractor
18
. Subtractor
18
then subtracts the re-converted voltage from DAC
16
from the sampled analog voltage from sample-and-hold amplifier
12
, producing a difference or residue voltage. This residue voltage from subtractor
18
is then multiplied by 2
B
by amplifier
19
. The output voltage from amplifier
19
is thus scaled back up in magnitude for input to the next successive stage
10
′.
Each successive stage
10
′ generates another B digital bits of less significance than earlier stages
10
. For example, first stage
10
produces the B most-significant-bits (MSBs), while second stage
10
′ produces the next B MSB's. The last stage (not shown) produces the final B bits, the least-significant-bits (LSBs). Simple, inexpensive ADCs and DAC's can be used for ADC
14
and DAC
16
when B is just 1 or 2 bits.
Pipelining the ADC's stages allows for higher throughput, since new samples can be taken and converted for every stage in the pipeline. A 10-stage pipeline can operate in parallel on 10 different analog samples at a time. While such an ADC is useful, many stages are needed when higher precision is needed. For example, when B=1 bit per stage, 16-bit precision requires 16 stages
10
,
10
′. Long pipelines increase delays or latencies until a conversion is completed. The serial pipeline structure increases power, area, and cost for the ADC.
What is desired is an Analog/Digital converter that uses a pipelined structure. A shorter pipeline is desired to reduce latency and cost. It is desired to reduce the pipeline depth by re-using ADC stages. It is desired to recirculate analog signals within a stage of a pipelined ADC. It is desired to use low-precision, low-cost ADC and DAC elements in a stage yet still achieve high overall precision with just a few stages.
SUMMARY OF THE INVENTION
A pipelined recycling Analog-to-Digital Converter (ADC) has an analog sample input that receives an analog sample voltage. A first pipeline stage receives the analog sample voltage. It has an initial converter, a final converter, and a feedback loop that connects an output voltage of the final converter to an input of the initial converter during recycling clock periods.
The first pipeline stage generates more-significant digital bits representing the analog sample voltage and outputs a residue voltage after several of the recycling clock periods. A second pipeline stage receives the residue voltage from the first pipeline stage. It also has an initial converter, a final converter, and a feedback loop that connects an output voltage of the final converter to an input of the initial converter during the recycling clock periods.
The second pipeline stage generates lower-significance digital bits representing the analog sample voltage over several of the recycling clock periods. The initial and final converter each have an analog input that receives an analog voltage, an ADC element that converts the analog voltage to digital bits, and a digital-to-analog converter (DAC) element coupled to the ADC element. It converts the digital bits to an analog DAC voltage. A subtractor receives the analog voltage from the analog input and receives the analog DAC voltage. It generates a difference voltage. A multiplying amplifier increases a scale of the difference voltage to generate an output voltage. Thus the feedback loops in each pipeline stage recycle analog voltages through the initial and final converters over several recycling clock periods.
In further aspects of the invention a sampling switch is coupled between the analog sample input and the analog input of the initial converter in the first pipeline stage. It applies the analog sample voltage to the initial converter in response to a sampling clock before the recycling clock periods. An inter-stage switch is coupled between the first and second pipeline stages. It applies the output voltage from the final converter of the first pipeline stage to the analog input of the initial converter in the second pipeline stage in response to the sampling clock. Thus switches pass sample and residue voltages through the pipeline stages.
In still further aspects a feedback switch applies the output voltage from the final converter to the analog input of the initial converter in a same one of the pipeline stages when the sampling clock is not activating the sampling switch. Thus analog voltages are fed back to the initial converter within a pipeline stage during the recycling clock periods, but samples are passed between stages and not fed back within a pipeline stage when the sampling clock is activating the sampling switch.
In other aspects each pipeline stage has an intermediate switch coupled between the initial and final converters in a pipeline stage. It applies the output voltage from the initial converter to the analog input of the final converter.
In other aspects each of the recycling clock periods includes a PH
1
phase and a PH
2
phase. The initial converters generate digital bits during the PH
1
phase, while the final converters generate digital bits during the PH
2
phase. The intermediate switch is closed during the PH
2
phase, while the feedback switch is closed during the PH
1
phase. Thus the initial and final converters operate in alternate phases of the recycling clock periods.


REFERENCES:
patent: 4814767 (1989-03-01), Fernandez et al.
patent: 5070332 (1991-12-01), Kaller et al.
patent: 5184130 (1993-02-01), Mangelsdorf
pa

Affiliated with

Also associated with

Rating

Two-stage pipelined recycling analog-to-digital converter (ADC) does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Two-stage pipelined recycling analog-to-digital converter (ADC), we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Two-stage pipelined recycling analog-to-digital converter (ADC) will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2611452