Static information storage and retrieval – Powering
Reexamination Certificate
2001-05-24
2003-03-18
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Powering
C365S145000, C365S185230
Reexamination Certificate
active
06535446
ABSTRACT:
BACKGROUND OF THE INVENTION
Desirable power supply voltages are becoming lower and lower, tending towards three volts and even lower in some recent applications. The challenge that faces designers of ferroelectric memories is to design solutions that allow the memory cell transistors to operate in the saturation region even at these very low voltages. While advances have been made in ferroelectric thin film technology to enable these ferroelectric materials to operate at low power supply voltages, corresponding advances in ferroelectric memory circuit designs are required as well.
A typical two transistor, two capacitor (“2T/2C”) ferroelectric memory cell
10
is shown in FIG.
1
A. Ferroelectric memory cell
10
includes two ferroelectric capacitors Z
1
and Z
2
and two N-channel transistors M
1
and M
2
. A word line
12
is coupled to the gates of transistors M
1
and M
2
, and plate line
14
is coupled to the bottom electrode of ferroelectric capacitors Z
1
and Z
2
. The top electrodes of ferroelectric capacitor Z
1
and Z
2
are coupled to the source/drains of each of transistors M
1
and M
2
. Two complementary-bit lines
16
and
18
are coupled to the other source/drains of each of transistors M
1
and M
2
. Non-volatile data is stored as a complementary polarization vector in ferroelectric capacitors Z
1
and Z
2
. A typical one transistor, one capacitor (“1T/1C”) ferroelectric memory cell
20
is shown in FIG.
1
B. Ferroelectric memory cell
20
includes a ferroelectric capacitor Z
3
and an N-channel transistor M
3
. A word line
22
is coupled to the gate of transistor M
3
, and a plate line
24
is coupled to the bottom electrode of ferroelectric capacitor Z
3
. The top electrode of ferroelectric capacitor Z
3
is coupled to the source/drain of transistor M
3
. A bit line
26
is coupled to the other source/drain of transistor M
3
. Non-volatile data is stored as a polarization vector in ferroelectric capacitor Z
3
.
To ensure the proper operation of ferroelectric random access memory (“FRAM”) technology at low power supply voltages, in either a 1T/1C or 2T/2C architecture, the most critical point for retaining data in the ferroelectric capacitors is to make sure that the data that is written to the cell or read from the cell is at the full supply potential.
What is desired, therefore, is a ferroelectric boost circuit for use in either 1T/1C or 2T/2C ferroelectric memory architectures so that none of the limited power supply voltage is lost and the full power supply voltage is written to and read from each ferroelectric memory cell.
SUMMARY OF THE INVENTION
According to the present invention, a low voltage boost circuit suitable for use in a ferroelectric memory is realized implementing five N-channel devices and two ferroelectric capacitors. The voltage on a word line is boosted using charge sharing techniques in order to assure proper operation at lower power supply voltage conditions. In operation, the gate of an N-channel pass gate is boosted to supply a full VDD voltage on the bottom electrode of a ferroelectric capacitor, which capacitively couples into the word line for an efficient word line voltage boost. The advantages of the boost circuit of the present invention are that the circuit operates at low voltages, uses only seven small N-channel devices that can easily fit in pitch, uses no P-channel devices, therefore eliminating the need for large design rule spacings (well-to-well) and has a very fast response time.
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Hogan & Hartson LLP
Kubida, Esq. William J.
Lebentritt Michael S.
Meza, Esq. Peter J.
Nguyen Tuan T.
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