Two-stage ESD protection circuit with a secondary ESD...

Details Two-stage ESD protection circuit with a secondary ESD... Two-stage ESD protection circuit with a secondary ESD...

2001-07-13

2003-09-16

Huynh, Kim (Department: 2182)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000

Reexamination Certificate

active

06621673

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit. In particular, the present invention relates to speeding up the trigger-on rate of a secondary ESD protection circuit in a two-stage ESD protection system.
2. Description of the Related Art
As the semiconductor manufacturing process develops, ESD protection has become one of the most critical reliability issues for integrated circuits (IC). In particular, as semiconductor process advances into the deep sub-micron era, scaled-down devices, thinner gate oxides, lightly-doped drain regions (LDD), shallow trench isolation (STI) process and the metallic salicide process are more vulnerable in terms of ESD stress. Therefore, an efficient ESD protection circuit must be designed and placed on the I/O pad to clamp the overstress voltage across the gate oxide in the internal circuit.
FIG. 1A
shows a conventional two-stage ESD protection circuit in an integrated circuit (IC). In
FIG. 1A
, the field oxide device NF, which utilizes a field oxide segment as a gate oxide and has a higher ESD robustness, acts as a primary ESD protection circuit. NF is positioned near the I/O pad
12
and directly coupled between the I/O pad
12
and VSS, serving to conduct most of the ESD current from the I/O pad
12
to VSS. Nevertheless, the trigger-on voltage of NF during an ESD event is still too high, and the internal circuit
10
of the IC may suffer damage from ESD current during an ESD event. Therefore, a secondary ESD protection circuit between the internal circuit
10
and VSS, incorporated with a buffering resistor RL, clamps voltage received by the internal circuit
10
, as shown in FIG.
1
A. The secondary ESD protection circuit conventionally consists of a gate-grounded NMOS, such as the NMOS N
2
in FIG.
1
A. When a positive ESD stress pulses at the I/O pad
12
and VSS is grounded, N
2
will initially be triggered on to clamp the voltage at node
14
due to its lower trigger-on voltage. NF, which has a higher trigger-on voltage, will trigger on later to drain most of the ESD charge out of the I/O pad
12
while the voltage at node
16
is higher to a certain level. N
2
responds by clamping voltage and draining out smaller ESD current, and, therefore, the silicon area for N
2
can be much smaller than that for NF.
As the semiconductor manufacturing process develops, STI process becomes dominant to replace LOCOS (local oxidation) process in CMOS (complementary metal oxide semiconductor) process flow. Unlike the field oxide device built by LOCOS process, the field oxide device built by STI process has a much lower trigger-on rate. If NF in
FIG. 1A
is formed by STI process, its response is so slow that risks the internal circuit
10
to ESD damage. Therefore, the NF in
FIG. 1A
becomes unsuitable as semiconductor process advances into the deep sub-micron era.
A known design for a two-stage ESD protection circuit is to apply NMOS with the same threshold voltage to construct the primary ESD protection circuit and the secondary ESD protection circuit, such as the gate-grounded NMOS N
1
and N
2
in FIG.
1
B. In order to achieve the object of the secondary ESD protection circuit triggering prior to the primary ESD protection circuit, the channel length of N
2
is designed to be shorter than that of N
1
. Nevertheless, the difference of trigger-on rate built by varying the channel length of an NMOS is very limited. In other words, although N
1
and N
2
have different channel lengths, during an ESD event, N
2
can't be distinctly triggered on prior to N
1
. Therefore, the efficiency of a two-stage ESD protection circuit is lost and the ESD protection circuit as shown in
FIG. 1B
may have a lower ESD robustness.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an ESD design concept, which increases the trigger-on rate of a secondary ESD protection circuit and is especially suitable to ICs fabricated by STI process.
The two-stage electrostatic discharge (ESD) protection circuit of the present invention is suitable for an input/output (I/O) port and is coupled across a pad and a power rail. The two-stage ESD protection circuit comprises a primary ESD protection circuit, an ESD detection circuit, a resistor and a secondary ESD protection circuit. The primary ESD protection circuit is coupled between the pad and the power rail. The ESD detection circuit is also coupled between the pad and the power rail. The resistor is connected in series between the pad and an internal circuit. The secondary ESD protection circuit is coupled between the internal circuit and the power rail. At the beginning of an ESD event, the ESD detection circuit provides a trigger voltage to trigger on the secondary ESD protection circuit prior to the trigger-on of the primary ESD protection circuit, thereby clamping voltage received by the internal circuit.
Another two-stage ESD protection circuit suitable to an input/output (I/O) port according to the present invention is provided. The two-stage ESD protection circuit is coupled across a pad and a power rail, and comprises a primary ESD protection circuit, a resistor and a secondary ESD protection circuit. The primary ESD protection circuit is coupled between the pad and the power rail, comprising a general NMOS with a first threshold voltage. The resistor is connected in series between the pad and an internal circuit. The secondary ESD protection circuit is coupled between the internal circuit and the power rail, comprising a native NMOS with a second threshold voltage lower than the first threshold voltage. At the beginning of an ESD event, the native NMOS in the secondary ESD protection circuit is triggered on prior to the trigger-on of the general NMOS in the primary ESD protection circuit, thereby clamping voltage received by the internal circuit.
By utilizing the ESD detection circuit or the native NMOS, the difficulty of the prior art in separating the trigger-on times of the primary ESD protection circuit and the secondary ESD protection circuit can be overcome, and a two-stage ESD protection circuit with improved ESD robustness is obtained.


REFERENCES:
patent: 5528188 (1996-06-01), Au et al.
patent: 5565790 (1996-10-01), Lee
patent: 6125021 (2000-09-01), Duvvury et al.
patent: 6275089 (2001-08-01), Song et al.

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