Two-stage CMOS latch with single-wire clock

Details Two-stage CMOS latch with single-wire clock Two-stage CMOS latch with single-wire clock

1992-02-07

1992-10-13

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307451, 307291, 307279, 307571, 307572, 307576, 307480, 307481, H03K 3289, H03K 19017

Patent

active

051553821

ABSTRACT:
A master/slave latch circuit employs a single-wire clock, with the clock being applied to only N-channel transistors in the master latch and to only P-channel transistors in the slave latch so that a race-through condition is alleviated in the event of clock skew. The circuits are of ratioless operation, since P-channel transistors are used in each circuit to pull the high side to the supply voltage, and N-channel transistors are used on the low side to assure a zero voltage level. Input to each latch is to the gates of a P-channel pull-up and an N-channel pull-down, while the storage node is between the two clocked transistors. The level of the storage node is inverted and fed back to at transistor across one of the clocked transistors, the one on the high side for the master latch and the low side for the slave latch, and these feedback transistors are of a channel type to support the ratioless scheme.

REFERENCES:
patent: 4804867 (1989-02-01), Okitaka et al.

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