Boots – shoes – and leggings
Patent
1992-12-30
1997-04-22
Coleman, Eric
Boots, shoes, and leggings
364736, 364754, 364760, G06F 1500
Patent
active
056236832
ABSTRACT:
The present invention provides a method and apparatus for achieving m-bit.times.m-bit multiplication in two states with a minimum amount of hardware. The invention multiplies an m-bit multiplicand A by an m-bit multiplier B to produce a 2m-bit final product A.times.B. The multiplicand A has a most significant m/2 bits denoted by A.sub.H and a least significant m/2 bits denoted by A.sub.L. The multiplier B has a most significant m/2 bits denoted by B.sub.H and a least significant m/2 bits denoted by B.sub.L. By adding the least significant m/2 bits of B.sub.H .times.A.sub.L to the middle m/2 bits of the product B.sub.L .times.A, the invention produces a number having a least significant m bits that are the least significant m bits of the final product during a first pass. The most significant m bits of the final product are produced during a second pass. Using this technique, the invention produces the final product in two states with substantially less hardware than current systems.
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Coleman Eric
Follansbee John
Intel Corporation
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