Television – Camera – system and detail – Solid-state image sensor
Reissue Patent
2001-06-29
2004-04-20
Garber, Wendy R. (Department: 2612)
Television
Camera, system and detail
Solid-state image sensor
C348S241000, C348S308000, C348S294000, C348S300000, C348S301000, C348S302000, C348S307000, C348S309000, C348S310000, C348S295000, C250S208100, C327S247000, C327S280000, C327S287000
Reissue Patent
active
RE038499
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to an output amplifier for an active pixel sensor cell array. More particularly, the invention pertains to an output amplifier for an active pixel sensor cell array, the amplifier having a two-stage design that reduces fixed pattern noise in the image data output from the array.
DESCRIPTION OF THE RELATED ART
Charge-coupled devices (CCDs) have been the mainstay of conventional imaging circuits for converting photons incident at individual pixel sensor cells (of a pixel sensor cell array) into electrical signals indicative of the intensity of light energy incident at each cell. In general, a CCD uses a photogate to convert light energy incident at a cell into an electrical charge, and a series of electrodes to transfer the charge collected at the photogate to an output sense node.
Although CCDs have many strengths, including high sensitivity and fill-factor, CCDs also suffer from a number of weaknesses. These weaknesses include limited readout rates and dynamic range limitations, and notably, the difficulty in integrating CCDs with CMOS-based microprocessors.
To overcome the limitations of CCD-based imaging circuits, imaging circuits have been developed which use active pixel sensor cells to convert pixels of light energy into electrical signals. An active pixel sensor cell typically includes a conventional photodiode and a number of transistors which provide amplification, readout control, and reset control in addition to producing the electrical signal output from the cell.
FIG. 1
is an example of two identical CMOS active pixel sensor cells (
10
and
11
) having conventional design, connected along a column of an active pixel sensor cell array, and circuitry
21
for use in reading all cells connected along the column.
As shown in
FIG. 1
, cell
10
includes photodiode d
1
(connected as shown between ground and Node
3
), and reset transistor N
1
. Transistor N
1
is an NMOS transistor whose drain is connected to a power supply node (Node
1
) maintained at potential V
cc
, whose source is connected to Node
3
, and whose gate is connected to Node
2
. The gate of transistor N
1
is controlled (in a manner to be described below) by a RESET voltage supplied to Node
2
.
Cell
10
also includes buffer transistor N
2
and row select transistor N
3
, each of which is an NMOS transistor. Transistor N
2
has a drain connected to Node
1
, a source connected to Node
4
, and a gate connected to Node
3
. Transistor N
3
has a drain connected to Node
4
, a source connected to Node
6
, and a gate connected to Node
5
. The gate of transistor N
3
is controlled (in a manner to be described below) by a ROW SELECT voltage supplied to Node
5
.
As shown in
FIG. 1
, circuitry
20
includes detection and calculation circuit
21
whose input terminal is connected to Node
6
. Circuit
21
includes a sense amplifier which outputs digital data indicative of light intensity incident at each selected cell along the column in response to voltages at Node
6
during a sampling period when each such cell is selected. Circuit
21
typically also implements correlated double sampling (“CDS”) or another post-processing method on the digital data output from the sense amplifier.
In normal operation, circuit
21
receives a sequence of voltages at Node
6
(which node is common to all cells connected along the column), with each pair of consecutive voltages being indicative of light intensity incident (during a sampling period) at a different one of the cells along the column.
Circuitry
20
also includes NMOS transistor N
6
(whose drain is connected to Node
6
and whose source is connected to ground) and a current mirror (comprising current source I
1
and NMOS transistors N
4
and N
5
connected as shown) which provides the necessary load for reading out the cells. Transistor N
5
of the current mirror preferably sinks no more than a small current (from Node
6
to ground), since fixed pattern noise resulting from mismatches in the channel lengths of the buffer transistors in the cells will increase with increasing current sunk by the current mirror.
The gate of transistor N
6
(at Node
8
) is controlled by a Column Reset signal. Use of a column reset transistor such as transistor N
6
is described in U.S. patent application Ser. No. 08/871,519 entitled “Active Pixel Sensor Cell that Reduces Noise in the Photo Information Extracted from the Cell,” filed on Jun. 9, 1997, naming Richard B. Merrill as inventor and assigned to the assignee of the present application.
Briefly, in operation of the
FIG. 1
array, transistor N
6
is used as a switch to place a defined voltage (ground potential) on Node
6
before circuit
21
reads one of the cells (e.g., cell
10
). Preferably, the gate of transistor N
6
is pulsed with a high level of column reset voltage “COLUMN RESET” prior to each pulsing of the row select voltage ROW SELECT. By pulsing the column select voltage COLUMN RESET just prior to each pulsing of the row select voltage ROW SELECT, the voltage at Node
6
is pulled to zero (ground potential) just prior to reading of the relevant one of the cells. When the voltage on Node
6
is set to zero immediately prior to pulsing the row select voltage, resulting noise (in the data determined by circuit
21
) is reduced substantially. For example, in one implementation of
FIG. 1
, the noise is reduced from approximately 15 mV (in the case that N
6
remains “off” at all times) to approximately one millivolt.
Also in accordance with the teaching of U.S. patent application Ser. No. 08/871,519 entitled “Active Pixel Sensor Cell that Reduces Noise in the Photo Information Extracted from the Cell,” filed Jun. 9, 1997, switch transistor N
6
is optionally replaced by a switch transistor whose channel terminals are connected between Node
6
and power supply Node
1
, and whose gate is coupled to receive the column select voltage COLUMN RESET. By pulsing the voltage COLUMN RESET just before each pulsing of the row select voltage, the switch transistor pulls up the voltage at Node
6
to voltage Vcc just prior to reading of each cell. This technique also reduces noise in the data determined by circuit
21
.
The operation of sampling (reading) each cell (e.g., cell
10
) begins by briefly pulsing the gate of the cell's reset transistor N
1
with a high level of reset voltage “RESET.” This high level of the reset voltage (typically equal to Vcc, where Vcc is typically 5 volts) resets the voltage on photodiode d
1
to an initial integration voltage to begin an image collection cycle.
Immediately after assertion of such pulse of the voltage signal “RESET,” the initial integration voltage on photodiode d
1
(the voltage at Node
3
) is V
ini
=VRESET−V
TN1
−V
CLOCK
, where V
TN1
is the threshold voltage of transistor N
1
, VRESET is the high level of the voltage signal “RESET,” and V
CLOCK
represents reset noise from the pulsed reset voltage (assumed to be constant). Similarly, the initial integration voltage at Node
4
is VRESET−V
TN1
−V
CLOCK
−V
TN2
, where V
TN2
is the threshold voltage of buffer transistor N
2
(functioning as a source follower).
After the reset voltage has been pulsed and the voltage on photodiode d
1
(the voltage at Node
3
) has been reset, the gate of transistor N
3
is pulsed with a high level of row select voltage signal “ROW SELECT.” The high level of the row select voltage causes the voltage at Node
4
, which represents the initial integration voltage of the cycle, to appear at Node
6
. Detection and calculation circuit
21
then amplifies, digitizes, and stores the value of the initial integration voltage as it appears at Node
6
.
Next, for a selected time period, photons are allowed to strike photodiode d
1
, thereby creating electron-hole pairs. Photodiode d
1
is designed to limit recombination between the newly formed electron-hole pairs.
As a result, the photogenerated holes are attracted to the ground terminal of photodiode d
1
, while the photogenerated electrons are attr
Brehmer Kevin
Merrill Richard B.
Foveon, Inc.
Garber Wendy R.
Sierra Patent Group Ltd.
Villecco John M.
LandOfFree
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