Two stage address decoder circuit for semiconductor memories

Details Two stage address decoder circuit for semiconductor memories Two stage address decoder circuit for semiconductor memories

1989-10-05

1991-06-04

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 307355, 36518902, 36523002, H03K 19086, H03K 1716, H03K 19092, H03K 19003

Patent

active

050216880

ABSTRACT:
A two stage address decoder circuit (AD) for 1/64 decode operation is disclosed which operates at high speed with low power consumption. Briefly stated, the circuit includes a first stage comprised of two predecoder circuits operable to develop predecoded output signals in response to input address signals and corresponding inverted address signals. Each predecoder circuit consists of a lower power high speed Differential Cascode Current Switch tree with its associated current source. The second or final decode stage is comprised of a plurality of final decoding circuits. Each final circuit consisting of a 2 way OR gate dynamically activated through a switched current source. The inputs of the 2 way OR gate are connected to one pair of the predecoded output signals. Final decoder circuits provide final decoded output signals which drive the word lines of a memory cell array. The switched current source is triggered by a control signal supplied by a clock generator (CG) so that the final decode circuits consume power only when the control signal is active.

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patent: 4823030 (1989-04-01), Wilhelm et al.
IBM Technical Disclosure Bulletin, vol. 26, No. 7A, Dec. 1983, pp. 3503-3504.
IEEE Journal of Solid-State Circuits, vol. 23, No. 1, Feb. 1988, pp. 68-73.

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