Two stage accumulator for use in updating coefficients

Details Two stage accumulator for use in updating coefficients Two stage accumulator for use in updating coefficients

1992-11-19

1994-04-26

Chin, Stephen

Pulse or digital communications

Repeaters

Testing

375 14, 3647242, 333 28R, H03K 5159

Patent

active

053073754

ABSTRACT:
A two stage accumulator is provided for updating coefficients. The accumulator is particularly useful in an adaptive equalizer. A first stage of the accumulator receives an error word and outputs sign and carry bits resulting from the addition of the error word and an N-bit LSB portion of a larger M-bit coefficient. A second stage is responsive to the sign and carry bits for updating the (M-N) MSB's of the M-bit coefficient. New error words are cyclically provided to the first stage during successive coefficient update cycles. The first stage can be implemented using an N-bit twos complement adder. The second stage can be implemented using an up/down counter. A leakage function is provided by causing the up/down counter to periodically skip over increment and decrement cycles.

REFERENCES:
patent: 3633105 (1972-01-01), Lender et al.
patent: 4580275 (1986-01-01), Pirani et al.
patent: 5134475 (1992-07-01), Johnston et al.

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