Two side decoding of a memory array

Details Two side decoding of a memory array Two side decoding of a memory array

2000-10-12

2002-04-16

Nelms, David (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S230060, C365S189080

Reexamination Certificate

active

06373742

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to memory devices and, more particularly, to decoding a memory array from two sides.
BACKGROUND
One type of memory device which has found wide commercial success in the electronics industry is commonly referred to as flash memory. This commercial success is due in part to the ability of flash memory devices to store electronic data over long periods of time without an electric power supply. In addition, flash memory devices can be erased and programmed by the end user after they are installed in an electronic device. This combined functionality is especially useful in electronic device applications, such as cellular telephones, personal digital assistants, and computer BIOS storage and other applications where power supply is intermittent and programmability is desired.
Flash memory devices are made up of an array of individual memory transistors, or cells, which are similar to those used in other types of memory devices. Flash memory devices, however, typically achieve their non-volatility of the memory cells by the addition of a floating gate between the control gate and the substrate region of the transistors. Like other memory devices, the transistors are oriented in rows and columns to form an array of transistors. As is common in the memory device art, the control gates of the memory cells in each row of the array are connected to a series of word lines, thus forming individual rows of cells that can be accessed by selecting the corresponding word line. Similarly, the drain regions of the cells in each column of the array are connected to a series of bit lines, thus forming individual columns of cells that can be accessed by selecting the corresponding bit lines. Finally, the source regions of each of the cells in the array are connected to a common source line. In some flash memory devices the array of transistors is subdivided into sectors of separate transistor arrays to provide added flexibility to the programming and erasing operations.
The data stored in each memory cell represents a binary 1 or 0, as is well-known in the art. To perform a program, read, or erase operation on a particular cell in the array, various predetermined voltages are applied to the control gate, drain region, and source region of the memory cell. By applying these predetermined voltages to a particular bit line column, a particular word line row, and the common source line, an individual cell at the intersection of the bit line and word line can be selected for reading or programming.
To program a cell, the control gate and the drain region of the cell are raised to predetermined programming voltages and the source is grounded. The voltages on the control gate and the drain region cause the generation of hot electrons which are injected onto the floating gate where they become trapped, forming a negative charge on the floating gate. This electron transfer mechanism is often referred to as Channel Hot Electron (CHE) injection. When the programming voltages are removed, the negative charge on the floating gate is maintained, thereby raising the threshold voltage. The threshold voltage is used during reading operations to determine if the cell is in a charged state, that is programmed, or whether the cell is in an uncharged state, that is un-programmed.
Cells are read by applying a predetermined voltage to the control gate and the drain region and grounding the source of the cell. The current in the bit line is then sensed with a sense amplifier. If the cell is programmed, the threshold voltage will be relatively high and the bitline current will be zero or at least relatively low, thus registering a binary 0. On the other hand if the cell is erased, the threshold voltage will be relatively low and the bit line current will be relatively high, thus registering a binary 1.
In contrast to the programming procedure, flash memory devices are typically bulk-erased by simultaneously erasing all the cells in a memory sector. One procedure for erasing an entire memory sector involves applying predetermined voltages to the common source line and all the word lines of the sector while the drain regions of the cells are left to float. This causes electron tunneling from the floating gate to the source region through Fowler-Nordheim (F-N) tunneling, which removes the negative charge from the floating gate of each of the cells in the memory sector.
Typically, the memory device is provided with a number of address pins that allow the user to specify individual groups of memory cells for various operations. As is well-known in the art, the number of address pins usually provided for selecting the rows of cells is equal to 2
x
, where x is the number of word lines in the memory device. Similarly, the number of address pins usually provided for selecting column groups of cells is equal to 2
y
, where y is the number of bytes or words in each row of cells (a byte being eight cells and a word being sixteen cells). When the memory device is performing internal embedded functions, the address bits for the row and column bits will sometimes be generated by a state machine within the memory device instead of being provided by the user through the address pins. The memory device also provides a number of data pins for input and output of the memory cell data. In a simple memory device, the number of data pins is equal to the number of column groups of cells that are selected by the column address bits.
In order to translate the row and column address bits into the specific word lines and bit lines that must be selected for an operation, an X-decoder and a Y-decoder are usually provided in the memory device. As is well-known in the art, the X-decoder receives the row address bits and connects the particular word line that corresponds to the address signal to the appropriate circuits. For example, in the case of a reading operation, the X-decoder will connect the selected word line to a voltage boosting circuit. Likewise, the Y-decoder receives the column address bits and connects the particular bit lines that correspond to the address signal to the appropriate circuits. In reading operations, the Y-decoder will connect each of the selected bit lines to a sense amplifier.
As is well-known in the memory device art, manufacturers of memory devices prefer circuit designs that are small and compact. One reason for this desire is the high fixed expense associated with manufacturing memory devices. By designing memory devices that are smaller, manufacturers can manufacture more memory devices with the same equipment, thus lowering the average cost of the memory devices. On the other hand, compact circuit designs also allow more circuits to be placed on a memory device without increasing the size of the memory device, thus improving the performance of the memory device without increasing the cost of the memory device. Accordingly, manufacturers desire circuit designs that optimize the layout of the circuits in the memory device by minimizing the space required by the circuits.
SUMMARY
A decoder is provided for decoding address bits from two sides of a memory array. In one embodiment, routing lines for the word lines of the memory array alternately extend from the left side and the right side of the array. Driver circuits that are connected to each of the word lines are positioned on both sides of the memory array. Because the vertical space required for the routing lines that are connected to the driver circuits is reduced, the width of the decoder can be reduced by providing additional rows of driver circuits with fewer driver circuits in each row.


REFERENCES:
patent: 5896344 (1999-04-01), Kirsch et al.
patent: 5940315 (1999-08-01), Cowles
patent: 6212090 (2001-04-01), Akita et al.
patent: 362192094 (1987-08-01), None

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