Two's complement subtracting system

Details Two's complement subtracting system Two's complement subtracting system

1975-05-19

1976-08-17

Atkinson, Charles E.

Registers

Transfer mechanism

Traveling pawl

G06F 7385

Patent

active

039756246

ABSTRACT:
A two's complement subtractor using a one bit full adder for the most significant bit. A series of arithmetic logic units are fed by the respective binary bits to be subtracted with the logic units effecting internal two's complementing of the subtrahend thereby permitting adding to the minuend. The most significant input bits are in addition fed to a one bit full adder together with the carry in bit from the last arithmetic logic unit of the series. The one bit full adder outputs the most significant bit or the sign resulting from the subtraction and this adder can have either internal inversion of the subtrahend or an inverter can precede the subtrahend input.

REFERENCES:
patent: 3196262 (1965-07-01), Thompson
patent: 3816734 (1974-06-01), Brendzel
Langdon, "Subtraction by Minuend Complementation", IEEE Trans. on Comp., Jan. 1969, pp. 74-76.

Affiliated with

Also associated with

Rating

Two's complement subtracting system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Two's complement subtracting system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Two's complement subtracting system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1487660