Two's complement pulse width modulator and method for pulse widt

Pulse or digital communications – Pulse width modulation

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370 9, 332109, H03K 708

Patent

active

054286395

ABSTRACT:
A pulse width modulator (PWM) (20) receives a two's complement input number and separates a sign bit from remaining less significant bits. The PWM converts these bits into an unsigned number in dependence on the sign bit. A comparator (41) provides a compare output signal in response to an output of a counter (30) equaling the unsigned number. An output circuit (25) provides first and second pulse width modulated signals for a length of time determined by the output of the comparator (41) in dependence on whether the sign bit indicates a positive or negative sign. In one embodiment, the PWM (20) converts a negative two's complement number to the unsigned number by one's complementing the least significant bits, and the output circuit (25) keeps the second pulse width modulated signal active for one additional clock cycle to fully convert to two's complement form, without the need for a carry operation.

REFERENCES:
patent: 3510780 (1970-05-01), Buehrle
patent: 4502024 (1985-02-01), Nishikawa et al.
patent: 4550307 (1985-10-01), Akashi et al.
patent: 5021788 (1991-06-01), Ueki et al.
patent: 5070312 (1991-12-01), Cho
patent: 5231363 (1993-07-01), Sano et al.
patent: 5298871 (1994-03-01), Shimohara

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