Two's complement multiplication with a sign magnitude multiplier

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G06F 752

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active

049263714

ABSTRACT:
A multi-bit overlapped scanning multiplication system using overlapped partial products in a matrix, accepts and multiplies either sign-magnitude operands or signed binary operands without correction, conversion, or complementation of operands or results.

REFERENCES:
patent: 3617723 (1971-11-01), Melvin
patent: 3730425 (1973-05-01), Kindell et al.
patent: 3737638 (1973-06-01), Esteban
patent: 3805043 (1974-04-01), Clary
patent: 3866030 (1975-02-01), Baugh et al.
patent: 4130878 (1978-12-01), Balph et al.
patent: 4507749 (1985-03-01), Ohhashi
patent: 4594679 (1986-06-01), George et al.
patent: 4718031 (1988-01-01), Nukiyama
patent: 4748582 (1988-05-01), New et al.
patent: 4796218 (1989-01-01), Tanaka et al.
patent: 4796219 (1989-01-01), Williams
C. S. Wallace, "A Suggestion for a Fast Multiplier", IEEE Trans. on Electronic Computers, Feb. 1964, pp. 14-17.
IEEE Transactions article by Charles R. Baugh et al., vol. C-22, No. 12, pp. 1045-1047, Dec. 1973 entitled "A Two's Complement Parallel Array Multiplication Algorithm".
IEEE Transactions article by Stylianos D. Pezaris, Apr. 1971, entitled "A 40-NS 17-Bit by 17-Bit Array Multiplier", pp. 442-447.

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