Two-ROM multibyte microcode address selection method and apparat

Details Two-ROM multibyte microcode address selection method and apparat Two-ROM multibyte microcode address selection method and apparat

1991-06-13

1995-09-19

Rudolph, Rebecca L.

Boots, shoes, and leggings

364DIG1, 364DIG2, 3642599, 3642446, 36426281, 39542102, G06F 930

Patent

active

054524237

ABSTRACT:
An efficient organization for microcoded instruction sets which have processor operations in which not all the bits of an instruction word are required. The organization has two registers for receiving and holding the first and second byte of instructions at a time, a first ROM connected to the register for decoding the first byte into control signals for operation of said microprocessor. One of these control signals is generated whenever the portion of the second instruction byte is required. The organization also has a second ROM connected to the register for decoding the portion of the second byte into control signals. Connected to said first and second ROMs is a multiplexer which selects the decoded second byte control signals for operation of the microprocessor responsive to the first ROM control signal. The combined size of the first and second ROMs is much smaller compared to that of a ROM which decodes both bytes all the time and achieves a great savings in the space occupied by the processor integrated circuit.

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Mano, Computer System Architecture, 2nd Ed., 1982, pp. 69-71.

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