Two-pin distributed ethernet bus architecture

Details Two-pin distributed ethernet bus architecture Two-pin distributed ethernet bus architecture

1999-01-08

2000-05-09

Follansbee, John A.

Electrical computers and digital processing systems: multicomput

Computer-to-computer data routing

Decentralized controlling

709225, 709250, H04B 336

Patent

active

060617373

ABSTRACT:
An intermodule network bus architecture using only two bus wires to transmit data and module state information. A two-pin bus interface in each network module connected to the bus provides for a distributed arbitration procedure in the event that two or more modules are competing for bus access, and provides a coding scheme under which both data signals and collision announcements are transmitted from module to module through the two-wire bus. The architecture handles multiple distributed repeater modules, as well as other network components such as bridges and routers connected to the same bus. An important aspect of the invention is that multiple bus interfaces function as a distributed state machine, to handle the arbitration process and to provide a consistent framework for detecting and processing data signals and various types of collisions, including receive collisions detected on a single local module port, and transmit collisions involving activity on multiple local ports of one or more modules.

REFERENCES:
patent: 4418386 (1983-11-01), Vrielink
patent: 5301303 (1994-04-01), Abraham et al.
patent: 5430762 (1995-07-01), Vijeh et al.
patent: 5452308 (1995-09-01), Kaminski et al.

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