Two-phase non-overlapping clock generator

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307262, 307480, H03K 513, H03K 1900

Patent

active

048167002

ABSTRACT:
An external timing source (40) provides an input waveform (44, 46) of signal voltage transitions which occur at a first frequency, which is twice the frequency desired by the internal clock. A divider circuit (48) divides the input waveform (44, 46) into a pair of intermediate waveforms (60, 62). The intermediate waveforms have signal-voltage transitions of opposing polarity which occur at a second frequency that is one-half of the first frequency. The input waveforms and the intermediate waveforms are supplied to a driver circuit (64). The driver circuit utilizes the intermediate waveforms occurring at the divided-down frequency and the input waveform occurring at the system clock frequency to produce a pair of final waveforms (66, 68). The final waveforms have signal voltage transistions of opposing polarity occurring at the divided-down frequency, but triggerred by and in synchronism with the input waveform occurring at the external clock frequency.

REFERENCES:
patent: 3596188 (1971-07-01), Hasse
patent: 3961269 (1976-06-01), Alvarez, Jr.
patent: 4417158 (1983-11-01), Ito et al.
patent: 4587441 (1986-05-01), Torelli et al.
patent: 4686386 (1987-08-01), Tadao

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