Two-phase MOS synchronizer

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307205, 307279, H03K 1908, H03K 326

Patent

active

039354750

ABSTRACT:
An MOS circuit synchronizes an asynchronous input signal to first and second alternating clock pulses in an integrated circuit system employing clocked ratio logic. A bistable device, such as a flip-flop, has first and second complementary inputs for establishing the state of the device and an output reflecting the state of the device. An input circuit for the bistable device receives the asynchronous signal and applies the signal to the first complementary input and the inverted asynchronous signal to the second complementary input. In addition, the input circuit has gate logic, implemented with field effect transistors, which decouples the asynchronous input for all intervals of time except during the interval of the first clock pulse. An output circuit for the bistable device employs an inverter in series with a field effect transistor which is driven into condition only during the interval of the second clock pulse. The MOS synchronizer circuit thus insures that an output signal of usable logic level is generated for an input signal occuring at any time with respect to the clock pulses of a clocked ratio MOS system.

REFERENCES:
patent: 3114109 (1963-12-01), Melas
patent: 3145309 (1964-08-01), Bothwell et al.
patent: 3488478 (1970-01-01), Gilbert
patent: 3764920 (1973-10-01), Galcik et al.
patent: 3813563 (1974-05-01), Hatsukano et al.
patent: 3813564 (1974-05-01), Hatsukano et al.
patent: 3832578 (1974-08-01), Nomiya et al.
patent: 3840757 (1974-10-01), Nomiya et al.
patent: 3854059 (1974-12-01), Nomiya et al.
patent: 3870897 (1975-03-01), Hatsukano et al.

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