Electric power conversion systems – Current conversion – With voltage multiplication means
Reexamination Certificate
1999-11-09
2001-03-27
Han, Jessica (Department: 2838)
Electric power conversion systems
Current conversion
With voltage multiplication means
C365S185330, C365S218000
Reexamination Certificate
active
06208539
ABSTRACT:
RELATED APPLICATION
This application is related to co-pending U.S. patent application Ser. No. 09/041,873, entitled “A Two-Phase Charge Pump with Opposite Type MOS Transistor Gated Channels” and assigned to the assignee of the present invention, the contents of which are hereby incorporated by reference.
TECHNICAL FIELD
This invention relates to computer systems, and more particularly to a method and apparatus for providing a charge pump that is particularly useful for generating high voltages and high currents for erasing and programming flash electrically-erasable programmable read only memory arrays (Flash EEPROMs).
BACKGROUND
The use of computers has grown so extensive that the power used by these computers has become significant. In order to reduce the cost of operation as well as the consequent use of energy resources, a substantial move is underway to reduce such power usage. A major trend in the manufacture of personal computers is toward a reduction in the voltage level required to operate the integrated circuits which are used in the various components of those computers. A simultaneous trend is the desire to provide portable computers which are able to provide most of the abilities of desktop computers but are assembled in very small and light packages. This has led to attempts to reduce the power used by portable computers so that their battery life will be extended.
In order to reduce power consumption and extend battery life, much of the integrated circuitry used in personal computers is being designed to run at low voltage levels. This reduces the power usage and allows more components to be placed closer to one another. The circuitry and components used in portable computers typically are being designed to operate at voltages levels less than about 5V, with 3.3V and lower becoming more common. Lower voltages helps a great deal to reduce the power needs of personal computers.
However, the desire to offer more features in portable computers has led to an increase in the number of circuits used, thus requiring more power. Further, a number of such features require higher voltages to function properly. For example, one real convenience is the ability to change the basic input/output system (BIOS) of a computer as improvements in a computer or its peripherals occur. Historically, such changes have been accomplished by removing an electrically programmable read only memory (EPROM) device or similar circuit that provides a non-volatile read only memory for storing the BIOS code and replacing that circuit with a new circuit at additional cost. Further, this procedure is beyond the abilities of many computer users. Recently, “flash” electrically-erasable programmable read only memory (Flash EEPROM memory) has been used to store BIOS code. This type of non-volatile memory device may be reprogrammed by running a small update program without removing the circuitry from the computer. However, reprogramming Flash EEPROM memory requires approximately 12V to accomplish effectively. The lower voltage batteries provided in personal computers generally are not capable of programing and erasing Flash EEPROM memory.
Further, a relatively new form of long term random access storage has been devised using Flash EEPROM devices in large arrays to mimic hard disk drives. Flash EEPROM arrays provide a smaller and lighter functional equivalent of a hard disk drive which operates more rapidly and is less sensitive to physical damage. Such memory arrays are especially useful in portable computers where space is at a premium and weight is extremely important. However, Flash EEPROM memory arrays also require much higher voltages for writing and erasing data than can be provided directly by the batteries of most portable computers.
In situations in which batteries do not provide sufficient voltages, it has been typical to provide “charge pumps” to generate a higher voltage from the lower voltages available. In particular, for some single supply voltage Flash EEPROM memory devices, it is necessary to generate voltages greater than the device supply voltage (VCC) and/or voltages more negative than ground using such charge pumps. However, although such voltages charge pumps are able to increase the voltage to an appropriate level, most charge pumps do not provide sufficient current to generate the power for effectively erasing and programming Flash EEPROM memory without the use of very large capacitors, which utilize an inordinate mount of die space.
More particularly, the voltage required for the drain side of a Flash EEPROM memory cell during programming is typically about 5.0V to 5.5V, which is higher than the typical minimum power supply (VCC) value of 4.5V. The current required to program such a memory cell is relatively quite large, typically about 4mA for an 8-bit memory device. Since power consumption of devices is increasingly a concern, it is important that this relatively large current be produced efficiently.
It is also important that charge pumped voltages be produced efficiently. An efficient design can lead to usage of smaller capacitors with obvious advantages. For CMOS integrated circuits, prior charge pumps typically were constructed of switched MOSFET transistors and MOSFET capacitors using 4-phase clocking techniques to eliminate a voltage drop from one stage of the charge pump to the next. An example of one such prior art charge pump is shown in U.S. Pat. No. 5,432,469 to Tedrow, et al.
SUMMARY
This invention relates to computer systems, and more particularly to a method and apparatus for providing a charge pump that is particularly useful for generating high voltages and high currents for erasing and programming flash electrically-erasable programmable read only memory arrays (Flash EEPROMs). In particular, the invention includes an efficient method and circuit for generating a pumped voltage with no voltage drop from one stage to the next by using a simple two-phase clocking scheme and an auxiliary pump to gate a larger primary pump.
In one aspect, the invention includes a charge pump circuit including an input for receiving an input voltage to be pumped; an auxiliary charge pump, coupled to the input, and having a first and a second auxiliary channel, for alternately pumping the input voltage to a voltage Vcharge in excess of the input voltage in each of the first and second auxiliary channels; a primary charge pump, coupled to the input and to the first and second auxiliary channels of the auxiliary charge pump, and having a first and a second primary channel, for alternately pumping the input voltage to a voltage in excess of the input voltage in each of the first and second primary channels under the control of the first and second auxiliary channels; and an output, coupled to each of the first and second primary channels, to allow transmission of a voltage pumped charge through the first and second primary channels.
Advantages of the invention compared to a 4-phase charge pump: use of a simpler clock generator; easier layout of capacitors since only two clocks are used rather than four; no requirement for charging and discharging of auxiliary capacitors, thus resulting in higher power efficiency; and no net diode voltage drop from one stage to the next, as is the case with simpler charge pumps. The preferred embodiment also includes a feature that allows adjustment of the level of voltage pumping to accommodate higher voltage power supplies.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
REFERENCES:
patent: 5263000 (1993-11-01), Van Burskirk et al.
patent: 5282170 (1994-01-01), Van Burskirk et al.
patent: 5291446 (1994-03-01), Van Burskirk et al.
patent: 5301097 (1994-04-01), McDaniel
patent: 5406517 (1995-04-01), Chang et al.
patent: 5432469 (1995-07-01), Tedrow et al.
patent: 5612921 (1997-03-01), Chang et al.
patent: 5719807 (1998-02-01), Sali et al.
patent:
EON Silicon Devices, Inc.
Fish & Richardson P.C.
Han Jessica
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