Two pass erase for non-volatile storage

Details Two pass erase for non-volatile storage Two pass erase for non-volatile storage

2011-03-15

2011-03-15

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185240, C365S185300, C365S185110

Reexamination Certificate

active

07907449

ABSTRACT:
Techniques are disclosed herein for erasing non-volatile memory cells. The memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. In one implementation, the threshold voltages of the memory cells are not verified after the second erase. Soft programming after the second erase may be performed. The magnitude of the soft programming pulse may be determined based on the trial erase pulse. In one implementation, the memory cells'threshold voltages are not verified after the soft programming. Limiting the number of erase pulses and soft programming pulses saves time and power. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing.

REFERENCES:
patent: 2009/0180325 (2009-07-01), Ito
patent: 2009006485 (2009-01-01), None
International Search Report and Written Opinion dated Oct. 27, 2010, PCT Application No. PCT/US2010/029246.

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