Two-part synchronization scheme for digital video decoders

Television – Bandwidth reduction system – Data rate reduction

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348423, H04N 712

Patent

active

054520061

ABSTRACT:
A novel synchronization scheme for use in connection with digital signal video decoder comprises a pre-parser, a channel buffer, and a post-parser. The pre-parser synchronizes to a multiplexed system bitstream received from a fixed rate channel. The video bitstream component of a multiplexed system bitstream is then extracted and synchronized prior to being transferred bit-serially from the pre-parser to a channel buffer. The post-parser is coupled to the channel buffer and to a video decoder in a series configuration. The post-parser separates the various layers of video data from the video bitstream component. The post-parser performs a translation operation on the video bitstream component and converts the bitstream data into symbol data. The symbol data is subsequently processed by the video decoder so as to reconstruct an originally encoded picture or frame. Preferably, the multiplexed system bitstream data structure conforms to some format agreed upon among video digital businesses involved in transmission and reception. In accordance with one aspect of the present invention, the pre-parser and the post-parser operate independent of each other, and operate at different processing rates.

REFERENCES:
patent: 4660079 (1987-04-01), Devimeux et al.
patent: 5202761 (1993-04-01), Cooper
patent: 5351090 (1994-09-01), Nakamura
patent: 5351092 (1994-09-01), Poimboeuf et al.
Moving Pictures Experts Group, Coding of Moving Pictures and Associated Audio for Digital Storage Media at Up to about 1.5 Mbit/s (Nov. 25, 1991, 2-11172 Ed. Rev 1) pp. 2-E1.

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