Two parety memory access arbitrator

Details Two parety memory access arbitrator Two parety memory access arbitrator

1990-06-20

1992-07-28

Safourek, Benedict V.

Multiplex communications

Wide area network

Packet switching

3408255, H04J 302

Patent

active

051346133

ABSTRACT:
A controller for use in a local area network includes an arbitration circuit that permits data communication between a processor and a buffer memory associated with the controller to take priority over data communication between controller and buffer memory. The arbitration circuit interrupts a controller-initiated read or write cycle upon the receipt of a read or write memory access request from the processor.

REFERENCES:
patent: 4819229 (1989-04-01), Pritty et al.
patent: 4858112 (1989-08-01), Puerzer et al.

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