Two-mask VJ-FET transistor structure

Details Two-mask VJ-FET transistor structure Two-mask VJ-FET transistor structure

1980-07-18

1981-10-20

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576W, 148187, 357 22, H01L 2120

Patent

active

042952670

ABSTRACT:
A simplified method of fabricating V-groove junction field effect transistors using only two masking steps. The first masking step opens regions in an ohmic refractory metal layer deposited on a doped semiconductor wafer. V-grooves are anisotropically etched into the wafer through the openings, thereby defining source and drain regions and outer isolation V-grooves. The wafer is then coated with a passivating layer. The second masking step creates openings through the passivation layer to the source and drain regions, and electrical contacts to those regions are made. An ohmic contact to the back surface of the wafer forms the gate electrode. Multiple source and drain regions may be created between the outer isolation V-grooves and electrically parallel for a greater current rating.

REFERENCES:
patent: 3930300 (1976-01-01), Nicolay
patent: 3975221 (1976-08-01), Rodgers
patent: 4003126 (1977-01-01), Holmes et al.

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