Two-loop line deflection system

Details Two-loop line deflection system Two-loop line deflection system

1985-04-01

1987-01-13

Ng, Jin F.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358150, H04N 504

Patent

active

046368612

ABSTRACT:
In a synchronized digital horizontal deflection system operating at 2.times.f.sub.H, a digital phase-lock-loop circuit generates first f.sub.H rate signal that is synchronized to the horizontal sync pulses, and a second f.sub.H rate second signal that is delayed from the first signal by one-half of the period H. A digital phase-control-loop circuit receives the first and second signals and generates a horizontal deflection control signal at 2.times.f.sub.H rate that controls the retrace interval timing in a deflection circuit output stage. The synchronization of every other retrace interval occur in accordance with information provided by the first signal.

REFERENCES:
patent: 4292654 (1981-09-01), Steckler et al.
patent: 4317133 (1982-02-01), Fernsler et al.
patent: 4327376 (1982-04-01), Balaban et al.
patent: 4351001 (1982-09-01), McGinn et al.
patent: 4467359 (1984-08-01), Hosoya
patent: 4476490 (1984-10-01), Kaneko
patent: 4591910 (1986-05-01), Lai et al.
Development Sample Data Sheet for MAA 2500 (DPU), pp. 109-127, of Digit 2000 VLSI Digital TV System, edition 1983/9.

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