Two-level transistor structures and method utilizing minimal are

Details Two-level transistor structures and method utilizing minimal are Two-level transistor structures and method utilizing minimal are

1984-06-18

1986-06-10

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29576B, 29577R, 148 15, 357 42, 357 59, 357 239, H01L 2978, H01L 21425

Patent

active

045934533

ABSTRACT:
The invention relates to the process for manufacturing and the structure of stacked transistors on a silicon substrate wherein a polysilicon layer is employed which is recrystallized and delineated to form the gate for one transistor and the source, channel and drain for the complementary transistor which is totally formed using isolating field oxide as its substrate.

REFERENCES:
patent: 4057824 (1977-11-01), Woods
patent: 4106045 (1978-08-01), Nishi
patent: 4160260 (1979-07-01), Weitzel et al.
patent: 4466172 (1984-08-01), Batra
patent: 4517729 (1985-05-01), Batra
Translation of Wada JA54-97384.
Translation of Iizuka JA55-62771.

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