Two level transistor formation for optimum silicon utilization

Details Two level transistor formation for optimum silicon utilization Two level transistor formation for optimum silicon utilization

1997-01-27

1999-07-20

Bowers, Charles

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

438145, 438152, 438175, H01L 2100

Patent

active

059266937

ABSTRACT:
A semiconductor process in which a trench transistor is formed between a pair of planar transistors such that the source/drain regions of the trench transistor are shared with the source/drain regions of the planar transistors. A substrate is provided and first and second planar transistors are formed upon the upper surface of the substrate. The gate dielectric of the trench transistor is vertically displaced below the upper surface of the substrate. The trench transistor shares a first shared source/drain structure with the first planar transistor and a second shared source/drain structure with the second planar transistor. The formation of the trench transistor preferably includes the steps of etching a trench into the substrate, thermally oxidizing a floor of the trench to form a trench gate dielectric, and filling the trench with a conductive material to form a trench gate structure. The trench floor is vertically displaced below the upper surface of the substrate by a trench depth. The trench depth is preferably greater than a junction depth of the source/drain structures. In one embodiment, the formation of the trench transistor further includes, prior to the thermal oxidation of the trench floor, forming first and second ldd structures within the first and second trench ldd regions of the substrate. The first and second trench ldd structures provide conductive paths that extend from a trench channel region located beneath the trench floor to the first and the second shared source/drain structures respectively.

REFERENCES:
patent: 5672891 (1997-09-01), Hammamoto et al.
patent: 5796143 (1998-08-01), Fulford, Jr. et al.

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