Two level system bus arbitration having lower priority multiproc

Multiplex communications – Wide area network – Packet switching

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Details

370 852, 370 856, 3642429, 36424292, 3642415, G06F 1336, G06F 1318

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active

053924363

ABSTRACT:
A method and apparatus for arbitrating between multiple processors that can be incorporated into an arbitration scheme that is designed to include only a single processor. The method includes consolidating the individual bus requests of each processor into a single bus request supplied to the single processor arbitration scheme. When control of the bus is allocated to the single processor, the multiprocessor arbitration arbitrates among the processors who requested the bus. The bus protocol used includes a least recently used method for granting bus access to the multiple processors coupled with a means for giving one processor priority over the others for access to the bus. The protocol also includes protection from interruption for the respective processor in control of the bus for a preset period of time.

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