Two-level protocol for multi-component bus ownership, and implem

Details Two-level protocol for multi-component bus ownership, and implem Two-level protocol for multi-component bus ownership, and implem

1990-10-01

1993-03-09

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, G06F 1200, G06F 1300

Patent

active

051931630

ABSTRACT:
A method and apparatus for monitoring transactions on a system bus for invalidate requests, including a queue for storing the invalidate requests which is divided into two parts. The first part of the queue is contained within a cache controller to ensure that an invalidate request is immediately available for processing when the cache controller is otherwise idle. The second part of the queue is contained within a system interface to ensure that the system interface can detect and respond to more system transactions before the first invalidate request has been processed and to enable the system interface to be immediately aware if the entire queue is full.

REFERENCES:
patent: 4142234 (1979-02-01), Bean et al.
patent: 4195340 (1980-03-01), Joyce et al.
patent: 4802085 (1989-01-01), Levy et al.
patent: 5003463 (1991-03-01), Coyle et al.
patent: 5019965 (1991-05-01), Webb, Jr. et al.
patent: 5025365 (1991-06-01), Mathur et al.
patent: 5058006 (1991-10-01), Durdan et al.
patent: 5072369 (1991-12-01), Theus et al.

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