Two-latch clocked-LSSD flip-flop

Details Two-latch clocked-LSSD flip-flop Two-latch clocked-LSSD flip-flop

2007-08-27

2009-02-17

Lam, Tuan T (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S203000, C327S208000, C327S218000

Reexamination Certificate

active

07492201

ABSTRACT:
A clocked level-sensitive scan design may have flip-flops designed to have data, scan-in, and output ports and to utilize two clock signals. Such a clocked level-sensitive scan flip-flop may be built utilizing two latches.

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