Two-latch clocked-LSSD flip-flop

Details Two-latch clocked-LSSD flip-flop Two-latch clocked-LSSD flip-flop

2007-08-28

2007-08-28

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S203000, C327S208000, C327S218000

Reexamination Certificate

active

10909382

ABSTRACT:
A clocked level-sensitive scan design may have flip-flops designed to have data, scan-in, and output ports and to utilize two clock signals. Such a clocked level-sensitive scan flip-flop may be built utilizing two latches.

REFERENCES:
patent: 4733405 (1988-03-01), Shimizume et al.
patent: 5469079 (1995-11-01), Mahant-Shetti et al.
patent: 5633606 (1997-05-01), Gaudet et al.
patent: 5760627 (1998-06-01), Gregor et al.
patent: 5784384 (1998-07-01), Maeno
patent: 5825224 (1998-10-01), Klass et al.
patent: 5999030 (1999-12-01), Inoue
patent: 6304122 (2001-10-01), Gregor et al.
patent: 6445235 (2002-09-01), Sachdev
patent: 2003/0025543 (2003-02-01), Itoh

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